URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_27/] [sim] - Rev 310

Rev	Log message	Author	Age	Path
310	More signals.	tadejm	7463d 06h	/ethmac/tags/rel_27/sim
309	Update file list files for different RAM models with byte select accessing.	tadejm	7463d 06h	/ethmac/tags/rel_27/sim
308	Moved RAM model file path from sim_file_list.lst to this file.	tadejm	7463d 06h	/ethmac/tags/rel_27/sim
299	Artisan RAMs added.	mohor	7570d 07h	/ethmac/tags/rel_27/sim
295	Few minor changes.	tadejm	7577d 05h	/ethmac/tags/rel_27/sim
294	Added path to a file with distributed RAM instances for xilinx.	tadejm	7579d 06h	/ethmac/tags/rel_27/sim
293	initial.	tadejm	7603d 03h	/ethmac/tags/rel_27/sim
292	Corrected mistake.	tadejm	7603d 03h	/ethmac/tags/rel_27/sim
291	initial	tadejm	7603d 04h	/ethmac/tags/rel_27/sim
290	Additional checking for FAILED tests added - for ATS.	tadejm	7603d 05h	/ethmac/tags/rel_27/sim
225	Some minor changes.	tadejm	7876d 04h	/ethmac/tags/rel_27/sim
224	Signals for a wave window in Modelsim.	tadejm	7876d 05h	/ethmac/tags/rel_27/sim
217	Bist supported.	mohor	7883d 05h	/ethmac/tags/rel_27/sim
215	Bist supported.	mohor	7883d 06h	/ethmac/tags/rel_27/sim
208	Virtual Silicon RAMs moved to lib directory	tadej	7901d 00h	/ethmac/tags/rel_27/sim
207	Virtual Silicon RAM support fixed	tadej	7901d 00h	/ethmac/tags/rel_27/sim
206	Virtual Silicon RAM added to the simulation.	mohor	7901d 00h	/ethmac/tags/rel_27/sim
205	ETH_VIRTUAL_SILICON_RAM supported.	mohor	7901d 01h	/ethmac/tags/rel_27/sim
187	_info file added.	mohor	7906d 23h	/ethmac/tags/rel_27/sim
186	Macro for testbench (DO file).	mohor	7907d 00h	/ethmac/tags/rel_27/sim