OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_3] - Rev 126

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
126 InvalidSymbol generation changed. mohor 7950d 06h /ethmac/tags/rel_3
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.		 mohor 7950d 06h /ethmac/tags/rel_3
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 7950d 07h /ethmac/tags/rel_3
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 7952d 08h /ethmac/tags/rel_3
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 7952d 08h /ethmac/tags/rel_3
120 Unused files removed. mohor 7952d 09h /ethmac/tags/rel_3
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7952d 09h /ethmac/tags/rel_3
118 ShiftEnded synchronization changed. mohor 7956d 00h /ethmac/tags/rel_3
117 Clock mrx_clk set to 2.5 MHz. mohor 7956d 11h /ethmac/tags/rel_3
116 Testing environment also includes traffic cop, memory interface and host
interface.		 mohor 7956d 11h /ethmac/tags/rel_3
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7957d 09h /ethmac/tags/rel_3
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7958d 06h /ethmac/tags/rel_3
113 RxPointer bug fixed. mohor 7964d 22h /ethmac/tags/rel_3
112 Previous bug wasn't succesfully removed. Now fixed. mohor 7965d 12h /ethmac/tags/rel_3
111 Master state machine had a bug when switching from master write to
master read.		 mohor 7966d 01h /ethmac/tags/rel_3
110 m_wb_cyc_o signal released after every single transfer. mohor 7966d 04h /ethmac/tags/rel_3
109 Comment removed. mohor 7966d 05h /ethmac/tags/rel_3
108 Testbench supports unaligned accesses. mohor 8033d 14h /ethmac/tags/rel_3
107 TX_BUF_BASE changed. mohor 8033d 14h /ethmac/tags/rel_3
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8033d 14h /ethmac/tags/rel_3
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.		 mohor 8042d 16h /ethmac/tags/rel_3
104 FCS should not be included in NibbleMinFl. mohor 8044d 10h /ethmac/tags/rel_3
103 Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is
selected in eth_defines.v		 mohor 8044d 10h /ethmac/tags/rel_3
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.		 mohor 8044d 11h /ethmac/tags/rel_3
101 Short frame and ReceivedLengthOK were not detected correctly. mohor 8044d 11h /ethmac/tags/rel_3
100 Generic ram or Xilinx ram can be used in fifo (selectable by setting
ETH_FIFO_XILINX in eth_defines.v).		 mohor 8044d 11h /ethmac/tags/rel_3
99 Document revised. mohor 8051d 10h /ethmac/tags/rel_3
98 Document revised. mohor 8051d 10h /ethmac/tags/rel_3
97 Small typo fixed. lampret 8068d 08h /ethmac/tags/rel_3
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.		 mohor 8072d 08h /ethmac/tags/rel_3

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.