OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_4/] - Rev 49

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
49 HASH0 and HASH1 register read/write added. mohor 8116d 06h /ethmac/tags/rel_4/
48 RxOverRun added to statuses. mohor 8116d 09h /ethmac/tags/rel_4/
47 HASH0 and HASH1 registers added. Registers address width was
changed to 8 bits.		 mohor 8116d 09h /ethmac/tags/rel_4/
46 HASH0 and HASH1 registers added. mohor 8116d 09h /ethmac/tags/rel_4/
45 Ethernet Datasheet added. mohor 8116d 16h /ethmac/tags/rel_4/
44 Ethernet Datasheet added to cvs. mohor 8116d 16h /ethmac/tags/rel_4/
43 Tx status is written back to the BD. mohor 8117d 17h /ethmac/tags/rel_4/
42 Rx status is written back to the BD. mohor 8120d 10h /ethmac/tags/rel_4/
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 8122d 12h /ethmac/tags/rel_4/
40 Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
MHz. Statuses, overrun, control frame transmission and reception still need
to be fixed.		 mohor 8123d 10h /ethmac/tags/rel_4/
39 Tx part finished. TxStatus needs to be fixed. Pause request needs to be
added.		 mohor 8127d 14h /ethmac/tags/rel_4/
38 Initial version. Equals to eth_wishbonedma.v at this moment. mohor 8136d 16h /ethmac/tags/rel_4/
37 Link in the header changed. mohor 8136d 16h /ethmac/tags/rel_4/
36 TX_BD_NUM register added instead of the RB_BD_ADDR. mohor 8182d 14h /ethmac/tags/rel_4/
35 RX_BD_NUM changed to TX_BD_NUM. Few typos corrected. mohor 8185d 11h /ethmac/tags/rel_4/
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).		 mohor 8185d 11h /ethmac/tags/rel_4/
33 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8185d 16h /ethmac/tags/rel_4/
32 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8185d 16h /ethmac/tags/rel_4/
31 RX_BD_NUM register added instead of the RB_BD_ADDR. mohor 8185d 17h /ethmac/tags/rel_4/
30 BD section updated. mohor 8187d 13h /ethmac/tags/rel_4/
29 Generic memory model is used. Defines are changed for the same reason. mohor 8207d 12h /ethmac/tags/rel_4/
28 New release. Name changed to lower case. mohor 8210d 03h /ethmac/tags/rel_4/
27 File names changed to lower case. mohor 8210d 04h /ethmac/tags/rel_4/
26 First release of product brief. mohor 8210d 04h /ethmac/tags/rel_4/
25 First release of product brief. mohor 8210d 04h /ethmac/tags/rel_4/
24 Log file added. mohor 8232d 15h /ethmac/tags/rel_4/
23 Number of addresses (wb_adr_i) minimized. mohor 8232d 15h /ethmac/tags/rel_4/
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.		 mohor 8232d 18h /ethmac/tags/rel_4/
21 Status signals changed, Adress decoding changed, interrupt controller
added.		 mohor 8233d 14h /ethmac/tags/rel_4/
20 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
demands).		 mohor 8257d 11h /ethmac/tags/rel_4/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.