Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_4/] [bench/] - Rev 116


Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
116 Testing environment also includes traffic cop, memory interface and host
mohor 6644d 11h /ethmac/tags/rel_4/bench/
108 Testbench supports unaligned accesses. mohor 6721d 15h /ethmac/tags/rel_4/bench/
107 TX_BUF_BASE changed. mohor 6721d 15h /ethmac/tags/rel_4/bench/
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
mohor 6766d 13h /ethmac/tags/rel_4/bench/
80 Small fixes for external/internal DMA missmatches. mohor 6787d 08h /ethmac/tags/rel_4/bench/
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 6797d 12h /ethmac/tags/rel_4/bench/
66 Testbench fixed, code simplified, unused signals removed. mohor 6797d 18h /ethmac/tags/rel_4/bench/
51 Added separate tests for Multicast, Unicast, Broadcast billditt 6799d 05h /ethmac/tags/rel_4/bench/
49 HASH0 and HASH1 register read/write added. mohor 6801d 05h /ethmac/tags/rel_4/bench/
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 6807d 11h /ethmac/tags/rel_4/bench/
36 TX_BD_NUM register added instead of the RB_BD_ADDR. mohor 6867d 13h /ethmac/tags/rel_4/bench/
23 Number of addresses (wb_adr_i) minimized. mohor 6917d 14h /ethmac/tags/rel_4/bench/
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 6917d 17h /ethmac/tags/rel_4/bench/
19 Defines changed (All precede with ETH_). Small changes because some
tools generate warnings when two operands are together. Synchronization
between two clocks domains in eth_wishbonedma.v is changed (due to ASIC
mohor 6942d 11h /ethmac/tags/rel_4/bench/
17 Signal names changed on the top level for easier pad insertion (ASIC). mohor 6982d 11h /ethmac/tags/rel_4/bench/
15 A define FPGA added to select between Artisan RAM (for ASIC) and Block Ram (For Virtex).
Include files fixed to contain no path.
File names and module names changed ta have a eth_ prologue in the name.
File eth_timescale.v is used to define timescale
All pin names on the top module are changed to contain _I, _O or _OE at the end.
Bidirectional signal MDIO is changed to three signals (Mdc_O, Mdi_I, Mdo_O
and Mdo_OE. The bidirectional signal must be created on the top level. This
is done due to the ASIC tools.
mohor 6991d 11h /ethmac/tags/rel_4/bench/
12 Directory structure changed. Files checked and joind together. mohor 6998d 04h /ethmac/tags/rel_4/bench/

powered by: WebSVN 2.1.0

© copyright 1999-2020, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.