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[/] [ethmac/] [tags/] [rel_4/] [rtl/] - Rev 140

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Rev	Log message	Author	Age	Path
140	Syntax error fixed.	mohor	7928d 02h	/ethmac/tags/rel_4/rtl
139	Synchronous reset added to all registers. Defines used for width. r_MiiMRst changed from bit position 10 to 9.	mohor	7928d 02h	/ethmac/tags/rel_4/rtl
138	Synchronous reset added.	mohor	7928d 02h	/ethmac/tags/rel_4/rtl
137	Defines for register width added. mii_rst signal in MIIMODER register changed.	mohor	7928d 02h	/ethmac/tags/rel_4/rtl
136	Parameter ResetValue changed to capital letters.	mohor	7928d 12h	/ethmac/tags/rel_4/rtl
134	Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No need to multiply or devide any more.	mohor	7930d 05h	/ethmac/tags/rel_4/rtl
133	- Busy signal was not set on time when scan status operation was performed and clock was divided with more than 2. - Nvalid remains valid two more clocks (was previously cleared too soon).	mohor	7930d 06h	/ethmac/tags/rel_4/rtl
132	LinkFailRegister is reflecting the status of the PHY's link fail status bit.	mohor	7930d 06h	/ethmac/tags/rel_4/rtl
131	LinkFail signal was not latching appropriate bit.	mohor	7930d 06h	/ethmac/tags/rel_4/rtl
129	Traffic cop with 2 wishbone master interfaces and 2 wishbona slave interfaces: - Host connects to the master interface - Ethernet master (DMA) connects to the second master interface - Memory interface connects to the slave interface - Ethernet slave interface (access to registers and BDs) connects to second slave interface	mohor	7930d 07h	/ethmac/tags/rel_4/rtl
127	WriteRxDataToMemory signal changed so end of frame (when last word is written to fifo) is changed.	mohor	7950d 06h	/ethmac/tags/rel_4/rtl
126	InvalidSymbol generation changed.	mohor	7950d 06h	/ethmac/tags/rel_4/rtl
125	RxAbort changed. Packets received with MRxErr (from PHY) are also aborted.	mohor	7950d 06h	/ethmac/tags/rel_4/rtl
122	ethernet spram added. So far a generic ram and xilinx RAMB4 are used.	mohor	7952d 08h	/ethmac/tags/rel_4/rtl
120	Unused files removed.	mohor	7952d 09h	/ethmac/tags/rel_4/rtl
119	Ram , used for BDs changed from generic_spram to eth_spram_256x32.	mohor	7952d 09h	/ethmac/tags/rel_4/rtl
118	ShiftEnded synchronization changed.	mohor	7956d 00h	/ethmac/tags/rel_4/rtl
115	RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.	mohor	7957d 08h	/ethmac/tags/rel_4/rtl
114	EXTERNAL_DMA removed. External DMA not supported.	mohor	7958d 05h	/ethmac/tags/rel_4/rtl
113	RxPointer bug fixed.	mohor	7964d 21h	/ethmac/tags/rel_4/rtl
112	Previous bug wasn't succesfully removed. Now fixed.	mohor	7965d 11h	/ethmac/tags/rel_4/rtl
111	Master state machine had a bug when switching from master write to master read.	mohor	7966d 00h	/ethmac/tags/rel_4/rtl
110	m_wb_cyc_o signal released after every single transfer.	mohor	7966d 04h	/ethmac/tags/rel_4/rtl
109	Comment removed.	mohor	7966d 04h	/ethmac/tags/rel_4/rtl
106	Outputs registered. Reset changed for eth_wishbone module.	mohor	8033d 14h	/ethmac/tags/rel_4/rtl
105	Compiler directives added. Tx and Rx fifo size incremented. A "late collision" bug fixed.	mohor	8042d 15h	/ethmac/tags/rel_4/rtl
104	FCS should not be included in NibbleMinFl.	mohor	8044d 09h	/ethmac/tags/rel_4/rtl
103	Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is selected in eth_defines.v	mohor	8044d 10h	/ethmac/tags/rel_4/rtl
102	Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled or not.	mohor	8044d 10h	/ethmac/tags/rel_4/rtl
101	Short frame and ReceivedLengthOK were not detected correctly.	mohor	8044d 10h	/ethmac/tags/rel_4/rtl

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[/] [ethmac/] [tags/] [rel_4/] [rtl/] - Rev 140

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