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[/] [ethmac/] [tags/] [rel_4/] [rtl/] [verilog/] [eth_registers.v] - Rev 338

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338 root 5476d 04h /ethmac/tags/rel_4/rtl/verilog/eth_registers.v
335 New directory structure. root 5533d 10h /ethmac/tags/rel_4/rtl/verilog/eth_registers.v
151 This commit was manufactured by cvs2svn to create tag 'rel_4'. 7911d 01h /ethmac/tags/rel_4/rtl/verilog/eth_registers.v
147 ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
the control frames connected.		 mohor 7911d 01h /ethmac/tags/rel_4/rtl/verilog/eth_registers.v
143 Only values smaller or equal to 0x80 can be written to TX_BD_NUM register.
r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.		 mohor 7927d 04h /ethmac/tags/rel_4/rtl/verilog/eth_registers.v
141 Syntax error fixed. mohor 7929d 21h /ethmac/tags/rel_4/rtl/verilog/eth_registers.v
140 Syntax error fixed. mohor 7929d 21h /ethmac/tags/rel_4/rtl/verilog/eth_registers.v
139 Synchronous reset added to all registers. Defines used for width. r_MiiMRst
changed from bit position 10 to 9.		 mohor 7929d 21h /ethmac/tags/rel_4/rtl/verilog/eth_registers.v
132 LinkFailRegister is reflecting the status of the PHY's link fail status bit. mohor 7932d 01h /ethmac/tags/rel_4/rtl/verilog/eth_registers.v
102 Interrupts are visible in the ETH_INT_SOURCE regardless if they are enabled
or not.		 mohor 8046d 06h /ethmac/tags/rel_4/rtl/verilog/eth_registers.v
74 Reset values are passed to registers through parameters mohor 8101d 03h /ethmac/tags/rel_4/rtl/verilog/eth_registers.v
69 Define missmatch fixed. mohor 8110d 06h /ethmac/tags/rel_4/rtl/verilog/eth_registers.v
68 Registered trimmed. Unused registers removed. mohor 8111d 06h /ethmac/tags/rel_4/rtl/verilog/eth_registers.v
56 File format fixed a bit. mohor 8112d 08h /ethmac/tags/rel_4/rtl/verilog/eth_registers.v
52 Modified for Address Checking,
addition of eth_addrcheck.v		 billditt 8112d 23h /ethmac/tags/rel_4/rtl/verilog/eth_registers.v
46 HASH0 and HASH1 registers added. mohor 8115d 03h /ethmac/tags/rel_4/rtl/verilog/eth_registers.v
37 Link in the header changed. mohor 8135d 09h /ethmac/tags/rel_4/rtl/verilog/eth_registers.v
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).		 mohor 8184d 05h /ethmac/tags/rel_4/rtl/verilog/eth_registers.v
32 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8184d 09h /ethmac/tags/rel_4/rtl/verilog/eth_registers.v
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.		 mohor 8231d 11h /ethmac/tags/rel_4/rtl/verilog/eth_registers.v

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