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[/] [ethmac/] [tags/] [rel_4/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 338

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338 root 5475d 08h /ethmac/tags/rel_4/rtl/verilog/eth_wishbone.v
335 New directory structure. root 5532d 13h /ethmac/tags/rel_4/rtl/verilog/eth_wishbone.v
151 This commit was manufactured by cvs2svn to create tag 'rel_4'. 7910d 04h /ethmac/tags/rel_4/rtl/verilog/eth_wishbone.v
150 Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
was not used OK.		 mohor 7910d 04h /ethmac/tags/rel_4/rtl/verilog/eth_wishbone.v
134 Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more.		 mohor 7931d 03h /ethmac/tags/rel_4/rtl/verilog/eth_wishbone.v
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.		 mohor 7951d 04h /ethmac/tags/rel_4/rtl/verilog/eth_wishbone.v
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7953d 07h /ethmac/tags/rel_4/rtl/verilog/eth_wishbone.v
118 ShiftEnded synchronization changed. mohor 7956d 22h /ethmac/tags/rel_4/rtl/verilog/eth_wishbone.v
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7958d 07h /ethmac/tags/rel_4/rtl/verilog/eth_wishbone.v
113 RxPointer bug fixed. mohor 7965d 20h /ethmac/tags/rel_4/rtl/verilog/eth_wishbone.v
112 Previous bug wasn't succesfully removed. Now fixed. mohor 7966d 10h /ethmac/tags/rel_4/rtl/verilog/eth_wishbone.v
111 Master state machine had a bug when switching from master write to
master read.		 mohor 7966d 23h /ethmac/tags/rel_4/rtl/verilog/eth_wishbone.v
110 m_wb_cyc_o signal released after every single transfer. mohor 7967d 02h /ethmac/tags/rel_4/rtl/verilog/eth_wishbone.v
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8034d 13h /ethmac/tags/rel_4/rtl/verilog/eth_wishbone.v
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.		 mohor 8043d 14h /ethmac/tags/rel_4/rtl/verilog/eth_wishbone.v
97 Small typo fixed. lampret 8069d 07h /ethmac/tags/rel_4/rtl/verilog/eth_wishbone.v
96 Any address can be used for Tx and Rx BD pointers. Address does not need
to be aligned.		 mohor 8073d 07h /ethmac/tags/rel_4/rtl/verilog/eth_wishbone.v
91 Comments in Slovene language removed. mohor 8079d 10h /ethmac/tags/rel_4/rtl/verilog/eth_wishbone.v
90 casex changed with case, fifo reset changed. mohor 8079d 10h /ethmac/tags/rel_4/rtl/verilog/eth_wishbone.v
88 rx_fifo was not always cleared ok. Fixed. mohor 8089d 07h /ethmac/tags/rel_4/rtl/verilog/eth_wishbone.v
87 Status was not latched correctly sometimes. Fixed. mohor 8089d 09h /ethmac/tags/rel_4/rtl/verilog/eth_wishbone.v
86 Big Endian problem when sending frames fixed. mohor 8090d 16h /ethmac/tags/rel_4/rtl/verilog/eth_wishbone.v
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.		 mohor 8096d 04h /ethmac/tags/rel_4/rtl/verilog/eth_wishbone.v
80 Small fixes for external/internal DMA missmatches. mohor 8100d 06h /ethmac/tags/rel_4/rtl/verilog/eth_wishbone.v
77 Interrupts changed mohor 8100d 07h /ethmac/tags/rel_4/rtl/verilog/eth_wishbone.v
64 Status was not written correctly when frames were discarted because of
address mismatch.		 mohor 8111d 06h /ethmac/tags/rel_4/rtl/verilog/eth_wishbone.v
61 RxStartFrm cleared when abort or retry comes. mohor 8111d 11h /ethmac/tags/rel_4/rtl/verilog/eth_wishbone.v
60 Changes that were lost when updating from 1.5 to 1.8 fixed. mohor 8111d 11h /ethmac/tags/rel_4/rtl/verilog/eth_wishbone.v
54 Addition of new module eth_addrcheck.v billditt 8112d 02h /ethmac/tags/rel_4/rtl/verilog/eth_wishbone.v
48 RxOverRun added to statuses. mohor 8114d 06h /ethmac/tags/rel_4/rtl/verilog/eth_wishbone.v

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