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Rev Log message Author Age Path
217 Bist supported. mohor 7198d 21h /ethmac/tags/rel_5
216 Bist signals added. mohor 7198d 21h /ethmac/tags/rel_5
215 Bist supported. mohor 7198d 22h /ethmac/tags/rel_5
214 Signals for WISHBONE B3 compliant interface added. mohor 7199d 18h /ethmac/tags/rel_5
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7199d 18h /ethmac/tags/rel_5
212 Minor $display change. mohor 7199d 18h /ethmac/tags/rel_5
211 Bist added. mohor 7199d 18h /ethmac/tags/rel_5
210 BIST added. mohor 7199d 18h /ethmac/tags/rel_5
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 7200d 21h /ethmac/tags/rel_5
208 Virtual Silicon RAMs moved to lib directory tadej 7216d 15h /ethmac/tags/rel_5
207 Virtual Silicon RAM support fixed tadej 7216d 15h /ethmac/tags/rel_5
206 Virtual Silicon RAM added to the simulation. mohor 7216d 15h /ethmac/tags/rel_5
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7216d 16h /ethmac/tags/rel_5
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7216d 16h /ethmac/tags/rel_5
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.
mohor 7216d 16h /ethmac/tags/rel_5
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 7219d 17h /ethmac/tags/rel_5
201 Core size added to the document. mohor 7219d 18h /ethmac/tags/rel_5
200 File with lower case checked in instead. mohor 7219d 18h /ethmac/tags/rel_5
199 Datasheet name changed to lower case name. mohor 7219d 18h /ethmac/tags/rel_5
198 Removed file. File with name in lower case will be added instead. mohor 7219d 18h /ethmac/tags/rel_5

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