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[/] [ethmac/] [tags/] [rel_5/] [rtl/] - Rev 133


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Rev Log message Author Age Path
133 - Busy signal was not set on time when scan status operation was performed
and clock was divided with more than 2.
- Nvalid remains valid two more clocks (was previously cleared too soon).
mohor 8010d 02h /ethmac/tags/rel_5/rtl/
132 LinkFailRegister is reflecting the status of the PHY's link fail status bit. mohor 8010d 02h /ethmac/tags/rel_5/rtl/
131 LinkFail signal was not latching appropriate bit. mohor 8010d 02h /ethmac/tags/rel_5/rtl/
129 Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
- Host connects to the master interface
- Ethernet master (DMA) connects to the second master interface
- Memory interface connects to the slave interface
- Ethernet slave interface (access to registers and BDs) connects to second
slave interface
mohor 8010d 03h /ethmac/tags/rel_5/rtl/
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.
mohor 8030d 02h /ethmac/tags/rel_5/rtl/
126 InvalidSymbol generation changed. mohor 8030d 02h /ethmac/tags/rel_5/rtl/
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
mohor 8030d 02h /ethmac/tags/rel_5/rtl/
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 8032d 04h /ethmac/tags/rel_5/rtl/
120 Unused files removed. mohor 8032d 05h /ethmac/tags/rel_5/rtl/
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 8032d 05h /ethmac/tags/rel_5/rtl/
118 ShiftEnded synchronization changed. mohor 8035d 20h /ethmac/tags/rel_5/rtl/
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 8037d 04h /ethmac/tags/rel_5/rtl/
114 EXTERNAL_DMA removed. External DMA not supported. mohor 8038d 02h /ethmac/tags/rel_5/rtl/
113 RxPointer bug fixed. mohor 8044d 18h /ethmac/tags/rel_5/rtl/
112 Previous bug wasn't succesfully removed. Now fixed. mohor 8045d 07h /ethmac/tags/rel_5/rtl/
111 Master state machine had a bug when switching from master write to
master read.
mohor 8045d 21h /ethmac/tags/rel_5/rtl/
110 m_wb_cyc_o signal released after every single transfer. mohor 8046d 00h /ethmac/tags/rel_5/rtl/
109 Comment removed. mohor 8046d 00h /ethmac/tags/rel_5/rtl/
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8113d 10h /ethmac/tags/rel_5/rtl/
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 8122d 12h /ethmac/tags/rel_5/rtl/

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