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[/] [ethmac/] [tags/] [rel_5/] [rtl/] - Rev 164

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Rev Log message Author Age Path
131 LinkFail signal was not latching appropriate bit. mohor 7897d 13h /ethmac/tags/rel_5/rtl/
129 Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
interfaces:
- Host connects to the master interface
- Ethernet master (DMA) connects to the second master interface
- Memory interface connects to the slave interface
- Ethernet slave interface (access to registers and BDs) connects to second
slave interface
mohor 7897d 14h /ethmac/tags/rel_5/rtl/
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.
mohor 7917d 13h /ethmac/tags/rel_5/rtl/
126 InvalidSymbol generation changed. mohor 7917d 13h /ethmac/tags/rel_5/rtl/
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.
mohor 7917d 13h /ethmac/tags/rel_5/rtl/
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 7919d 15h /ethmac/tags/rel_5/rtl/
120 Unused files removed. mohor 7919d 16h /ethmac/tags/rel_5/rtl/
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7919d 16h /ethmac/tags/rel_5/rtl/
118 ShiftEnded synchronization changed. mohor 7923d 07h /ethmac/tags/rel_5/rtl/
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7924d 15h /ethmac/tags/rel_5/rtl/

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