OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_5/] [rtl/] - Rev 166

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
133 - Busy signal was not set on time when scan status operation was performed
and clock was divided with more than 2.
- Nvalid remains valid two more clocks (was previously cleared too soon).
mohor 8093d 19h /ethmac/tags/rel_5/rtl/
132 LinkFailRegister is reflecting the status of the PHY's link fail status bit. mohor 8093d 19h /ethmac/tags/rel_5/rtl/
131 LinkFail signal was not latching appropriate bit. mohor 8093d 19h /ethmac/tags/rel_5/rtl/
129 Traffic cop with 2 wishbone master interfaces and 2 wishbona slave
interfaces:
- Host connects to the master interface
- Ethernet master (DMA) connects to the second master interface
- Memory interface connects to the slave interface
- Ethernet slave interface (access to registers and BDs) connects to second
slave interface
mohor 8093d 20h /ethmac/tags/rel_5/rtl/
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.
mohor 8113d 19h /ethmac/tags/rel_5/rtl/
126 InvalidSymbol generation changed. mohor 8113d 19h /ethmac/tags/rel_5/rtl/
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.
mohor 8113d 19h /ethmac/tags/rel_5/rtl/
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 8115d 21h /ethmac/tags/rel_5/rtl/
120 Unused files removed. mohor 8115d 22h /ethmac/tags/rel_5/rtl/
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 8115d 22h /ethmac/tags/rel_5/rtl/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.