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162 Another temporary version. Core is almost finished. Testbench not included,
mohor 7953d 07h /ethmac/tags/rel_6/
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.
mohor 7953d 12h /ethmac/tags/rel_6/
160 error acknowledge cycle termination added to display. mohor 7953d 12h /ethmac/tags/rel_6/
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.
mohor 7954d 09h /ethmac/tags/rel_6/
158 Typo fixed. mohor 7954d 09h /ethmac/tags/rel_6/
157 This testbench will soon be obsolete. Please use tb_ethernet.v mohor 7956d 14h /ethmac/tags/rel_6/
156 Valid testbench. mohor 7956d 14h /ethmac/tags/rel_6/
155 Minor changes. mohor 7956d 14h /ethmac/tags/rel_6/
154 Design document is still under construction. mohor 7957d 14h /ethmac/tags/rel_6/
153 Temp version (backup). mohor 7958d 05h /ethmac/tags/rel_6/
152 Version 1.16 created. See revision history in the document for details. mohor 7958d 05h /ethmac/tags/rel_6/
150 Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
was not used OK.
mohor 7958d 07h /ethmac/tags/rel_6/
149 Signals related to the control frames connected. Debug registers reg1, 2, 3, 4
mohor 7958d 07h /ethmac/tags/rel_6/
148 Bug when last byte of destination address was not checked fixed. mohor 7958d 07h /ethmac/tags/rel_6/
147 ETH_TXCTRL and ETH_RXCTRL registers added. Interrupts related to
the control frames connected.
mohor 7958d 07h /ethmac/tags/rel_6/
146 CarrierSenseLost status is not set when working in loopback mode. mohor 7958d 07h /ethmac/tags/rel_6/
145 Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL). mohor 7958d 07h /ethmac/tags/rel_6/
143 Only values smaller or equal to 0x80 can be written to TX_BD_NUM register.
r_TxEn and r_RxEn depend on the limit values of the TX_BD_NUMOut.
mohor 7974d 09h /ethmac/tags/rel_6/
141 Syntax error fixed. mohor 7977d 03h /ethmac/tags/rel_6/
140 Syntax error fixed. mohor 7977d 03h /ethmac/tags/rel_6/
139 Synchronous reset added to all registers. Defines used for width. r_MiiMRst
changed from bit position 10 to 9.
mohor 7977d 03h /ethmac/tags/rel_6/
138 Synchronous reset added. mohor 7977d 03h /ethmac/tags/rel_6/
137 Defines for register width added. mii_rst signal in MIIMODER register
mohor 7977d 03h /ethmac/tags/rel_6/
136 Parameter ResetValue changed to capital letters. mohor 7977d 13h /ethmac/tags/rel_6/
135 New revision. External DMA removed, TX_BD_NUM changed. mohor 7979d 05h /ethmac/tags/rel_6/
134 Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more.
mohor 7979d 06h /ethmac/tags/rel_6/
133 - Busy signal was not set on time when scan status operation was performed
and clock was divided with more than 2.
- Nvalid remains valid two more clocks (was previously cleared too soon).
mohor 7979d 07h /ethmac/tags/rel_6/
132 LinkFailRegister is reflecting the status of the PHY's link fail status bit. mohor 7979d 07h /ethmac/tags/rel_6/
131 LinkFail signal was not latching appropriate bit. mohor 7979d 07h /ethmac/tags/rel_6/
130 First draft of the Ethernet design document. Not a finished version. Still many
things missing.
mohor 7979d 07h /ethmac/tags/rel_6/

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