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139 Synchronous reset added to all registers. Defines used for width. r_MiiMRst
changed from bit position 10 to 9.
mohor 7981d 17h /ethmac/tags/rel_6/
138 Synchronous reset added. mohor 7981d 17h /ethmac/tags/rel_6/
137 Defines for register width added. mii_rst signal in MIIMODER register
mohor 7981d 17h /ethmac/tags/rel_6/
136 Parameter ResetValue changed to capital letters. mohor 7982d 03h /ethmac/tags/rel_6/
135 New revision. External DMA removed, TX_BD_NUM changed. mohor 7983d 19h /ethmac/tags/rel_6/
134 Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more.
mohor 7983d 20h /ethmac/tags/rel_6/
133 - Busy signal was not set on time when scan status operation was performed
and clock was divided with more than 2.
- Nvalid remains valid two more clocks (was previously cleared too soon).
mohor 7983d 21h /ethmac/tags/rel_6/
132 LinkFailRegister is reflecting the status of the PHY's link fail status bit. mohor 7983d 21h /ethmac/tags/rel_6/
131 LinkFail signal was not latching appropriate bit. mohor 7983d 21h /ethmac/tags/rel_6/
130 First draft of the Ethernet design document. Not a finished version. Still many
things missing.
mohor 7983d 21h /ethmac/tags/rel_6/

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