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[/] [ethmac/] [tags/] [rel_6/] - Rev 188

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Rev Log message Author Age Path
188 PHY changed. tadej 7897d 22h /ethmac/tags/rel_6
187 _info file added. mohor 7897d 23h /ethmac/tags/rel_6
186 Macro for testbench (DO file). mohor 7897d 23h /ethmac/tags/rel_6
185 Directory keeper. mohor 7897d 23h /ethmac/tags/rel_6
184 Modelsim simulation environment should be ready now. mohor 7898d 00h /ethmac/tags/rel_6
183 Modelsim environment added. mohor 7898d 00h /ethmac/tags/rel_6
182 Full duplex test improved. tadej 7899d 00h /ethmac/tags/rel_6
181 MIIM test look better. mohor 7899d 03h /ethmac/tags/rel_6
180 Bench outputs data to display every 128 bytes. mohor 7901d 23h /ethmac/tags/rel_6
179 Beautiful tests merget together mohor 7902d 00h /ethmac/tags/rel_6
178 Rearanged testcases mohor 7902d 00h /ethmac/tags/rel_6
177 Bug in MIIM fixed. mohor 7902d 03h /ethmac/tags/rel_6
176 lists changed to new directory structure mohor 7902d 05h /ethmac/tags/rel_6
175 Script fixed to new dir structure mohor 7902d 05h /ethmac/tags/rel_6
174 Directory keeper mohor 7902d 05h /ethmac/tags/rel_6
173 Keeps the directory mohor 7902d 05h /ethmac/tags/rel_6
172 NCSIM simulation environment added to cvs mohor 7902d 05h /ethmac/tags/rel_6
171 NCSIM simulation environment added. mohor 7902d 05h /ethmac/tags/rel_6
170 Headers changed. mohor 7902d 06h /ethmac/tags/rel_6
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 7902d 06h /ethmac/tags/rel_6
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7903d 03h /ethmac/tags/rel_6
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 7904d 04h /ethmac/tags/rel_6
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.		 mohor 7905d 04h /ethmac/tags/rel_6
165 HASH improvement needed. mohor 7905d 08h /ethmac/tags/rel_6
164 Ethernet debug registers removed. mohor 7905d 08h /ethmac/tags/rel_6
163 Another temporary version. Core is almost finished. Testbench not included,
yet"		 mohor 7906d 00h /ethmac/tags/rel_6
162 Another temporary version. Core is almost finished. Testbench not included,
yet.		 mohor 7906d 00h /ethmac/tags/rel_6
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.		 mohor 7906d 05h /ethmac/tags/rel_6
160 error acknowledge cycle termination added to display. mohor 7906d 05h /ethmac/tags/rel_6
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.		 mohor 7907d 02h /ethmac/tags/rel_6

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