URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_6/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 338

Rev	Log message	Author	Age	Path
106	Outputs registered. Reset changed for eth_wishbone module.	mohor	8033d 00h	/ethmac/tags/rel_6/rtl/verilog/eth_wishbone.v
105	Compiler directives added. Tx and Rx fifo size incremented. A "late collision" bug fixed.	mohor	8042d 01h	/ethmac/tags/rel_6/rtl/verilog/eth_wishbone.v
97	Small typo fixed.	lampret	8067d 18h	/ethmac/tags/rel_6/rtl/verilog/eth_wishbone.v
96	Any address can be used for Tx and Rx BD pointers. Address does not need to be aligned.	mohor	8071d 18h	/ethmac/tags/rel_6/rtl/verilog/eth_wishbone.v
91	Comments in Slovene language removed.	mohor	8077d 21h	/ethmac/tags/rel_6/rtl/verilog/eth_wishbone.v
90	casex changed with case, fifo reset changed.	mohor	8077d 21h	/ethmac/tags/rel_6/rtl/verilog/eth_wishbone.v
88	rx_fifo was not always cleared ok. Fixed.	mohor	8087d 18h	/ethmac/tags/rel_6/rtl/verilog/eth_wishbone.v
87	Status was not latched correctly sometimes. Fixed.	mohor	8087d 20h	/ethmac/tags/rel_6/rtl/verilog/eth_wishbone.v
86	Big Endian problem when sending frames fixed.	mohor	8089d 03h	/ethmac/tags/rel_6/rtl/verilog/eth_wishbone.v
82	Byte ordering changed (Big Endian used). casex changed with case because Xilinx Foundation had problems. Tested in HW. It WORKS.	mohor	8094d 15h	/ethmac/tags/rel_6/rtl/verilog/eth_wishbone.v