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[/] [ethmac/] [tags/] [rel_7/] - Rev 187

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Rev Log message Author Age Path
187 _info file added. mohor 7893d 21h /ethmac/tags/rel_7
186 Macro for testbench (DO file). mohor 7893d 21h /ethmac/tags/rel_7
185 Directory keeper. mohor 7893d 22h /ethmac/tags/rel_7
184 Modelsim simulation environment should be ready now. mohor 7893d 22h /ethmac/tags/rel_7
183 Modelsim environment added. mohor 7893d 22h /ethmac/tags/rel_7
182 Full duplex test improved. tadej 7894d 23h /ethmac/tags/rel_7
181 MIIM test look better. mohor 7895d 01h /ethmac/tags/rel_7
180 Bench outputs data to display every 128 bytes. mohor 7897d 21h /ethmac/tags/rel_7
179 Beautiful tests merget together mohor 7897d 22h /ethmac/tags/rel_7
178 Rearanged testcases mohor 7897d 22h /ethmac/tags/rel_7
177 Bug in MIIM fixed. mohor 7898d 02h /ethmac/tags/rel_7
176 lists changed to new directory structure mohor 7898d 03h /ethmac/tags/rel_7
175 Script fixed to new dir structure mohor 7898d 04h /ethmac/tags/rel_7
174 Directory keeper mohor 7898d 04h /ethmac/tags/rel_7
173 Keeps the directory mohor 7898d 04h /ethmac/tags/rel_7
172 NCSIM simulation environment added to cvs mohor 7898d 04h /ethmac/tags/rel_7
171 NCSIM simulation environment added. mohor 7898d 04h /ethmac/tags/rel_7
170 Headers changed. mohor 7898d 04h /ethmac/tags/rel_7
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 7898d 05h /ethmac/tags/rel_7
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7899d 02h /ethmac/tags/rel_7
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 7900d 02h /ethmac/tags/rel_7
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.		 mohor 7901d 03h /ethmac/tags/rel_7
165 HASH improvement needed. mohor 7901d 06h /ethmac/tags/rel_7
164 Ethernet debug registers removed. mohor 7901d 06h /ethmac/tags/rel_7
163 Another temporary version. Core is almost finished. Testbench not included,
yet"		 mohor 7901d 22h /ethmac/tags/rel_7
162 Another temporary version. Core is almost finished. Testbench not included,
yet.		 mohor 7901d 22h /ethmac/tags/rel_7
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.		 mohor 7902d 04h /ethmac/tags/rel_7
160 error acknowledge cycle termination added to display. mohor 7902d 04h /ethmac/tags/rel_7
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.		 mohor 7903d 00h /ethmac/tags/rel_7
158 Typo fixed. mohor 7903d 00h /ethmac/tags/rel_7

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