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[/] [ethmac/] [tags/] [rel_7/] [rtl/] - Rev 221


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Rev Log message Author Age Path
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7241d 20h /ethmac/tags/rel_7/rtl/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
mohor 7244d 20h /ethmac/tags/rel_7/rtl/
218 Typo error fixed. (When using Bist) mohor 7244d 22h /ethmac/tags/rel_7/rtl/
214 Signals for WISHBONE B3 compliant interface added. mohor 7245d 19h /ethmac/tags/rel_7/rtl/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7245d 19h /ethmac/tags/rel_7/rtl/
212 Minor $display change. mohor 7245d 19h /ethmac/tags/rel_7/rtl/
211 Bist added. mohor 7245d 19h /ethmac/tags/rel_7/rtl/
210 BIST added. mohor 7245d 20h /ethmac/tags/rel_7/rtl/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7262d 18h /ethmac/tags/rel_7/rtl/
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
mohor 7262d 18h /ethmac/tags/rel_7/rtl/
202 CsMiss added. When address between 0x800 and 0xfff is accessed within
Ethernet Core, error acknowledge is generated.
mohor 7265d 19h /ethmac/tags/rel_7/rtl/
168 CarrierSenseLost bug fixed when operating in full duplex mode. mohor 7273d 21h /ethmac/tags/rel_7/rtl/
167 Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed. mohor 7274d 22h /ethmac/tags/rel_7/rtl/
166 Reception is possible after RxPointer is read and not after BD is read. For
that reason RxBDReady is changed to RxReady.
Busy_IRQ interrupt connected. When there is no RxBD ready and frame
comes, interrupt is generated.
mohor 7275d 22h /ethmac/tags/rel_7/rtl/
165 HASH improvement needed. mohor 7276d 01h /ethmac/tags/rel_7/rtl/
164 Ethernet debug registers removed. mohor 7276d 01h /ethmac/tags/rel_7/rtl/
161 Error acknowledge is generated when accessing BDs and RST bit in the
MODER register (r_Rst) is set.
mohor 7276d 23h /ethmac/tags/rel_7/rtl/
160 error acknowledge cycle termination added to display. mohor 7276d 23h /ethmac/tags/rel_7/rtl/
159 Async reset for WB_ACK_O removed (when core was in reset, it was
impossible to access BDs).
RxPointers and TxPointers names changed to be more descriptive.
TxUnderRun synchronized.
mohor 7277d 20h /ethmac/tags/rel_7/rtl/
150 Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals
changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal
was not used OK.
mohor 7281d 17h /ethmac/tags/rel_7/rtl/

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