URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_7/] [rtl/] [verilog/] - Rev 109

Rev	Log message	Author	Age	Path
84	LinkFail signal was not latching appropriate bit.	mohor	8102d 21h	/ethmac/tags/rel_7/rtl/verilog/
83	MAC address recognition was not correct (bytes swaped).	mohor	8102d 21h	/ethmac/tags/rel_7/rtl/verilog/
82	Byte ordering changed (Big Endian used). casex changed with case because Xilinx Foundation had problems. Tested in HW. It WORKS.	mohor	8102d 23h	/ethmac/tags/rel_7/rtl/verilog/
80	Small fixes for external/internal DMA missmatches.	mohor	8107d 01h	/ethmac/tags/rel_7/rtl/verilog/
79	RetryCntLatched was unused and removed from design	mohor	8107d 02h	/ethmac/tags/rel_7/rtl/verilog/
78	WB_SEL_I was unused and removed from design	mohor	8107d 02h	/ethmac/tags/rel_7/rtl/verilog/
77	Interrupts changed	mohor	8107d 02h	/ethmac/tags/rel_7/rtl/verilog/
76	Interrupts changed in the top file	mohor	8107d 02h	/ethmac/tags/rel_7/rtl/verilog/
75	r_Bro is used for accepting/denying frames	mohor	8107d 02h	/ethmac/tags/rel_7/rtl/verilog/
74	Reset values are passed to registers through parameters	mohor	8107d 02h	/ethmac/tags/rel_7/rtl/verilog/