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[/] [ethmac/] [tags/] [rel_7/] [rtl/] [verilog/] [eth_defines.v] - Rev 211

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211 Bist added. mohor 7875d 02h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.		 mohor 7892d 00h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v
145 Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL). mohor 7911d 00h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v
137 Defines for register width added. mii_rst signal in MIIMODER register
changed.		 mohor 7929d 21h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v
134 Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more.		 mohor 7931d 23h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7954d 03h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v
106 Outputs registered. Reset changed for eth_wishbone module. mohor 8035d 08h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.		 mohor 8044d 10h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.		 mohor 8080d 06h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v
73 Number of interrupts changed mohor 8101d 03h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v
68 Registered trimmed. Unused registers removed. mohor 8111d 05h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8111d 06h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v
55 Changed that were lost with last update put back to the file. mohor 8112d 08h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v
52 Modified for Address Checking,
addition of eth_addrcheck.v		 billditt 8112d 22h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v
46 HASH0 and HASH1 registers added. mohor 8115d 02h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v
42 Rx status is written back to the BD. mohor 8119d 02h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v
40 Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200
MHz. Statuses, overrun, control frame transmission and reception still need
to be fixed.		 mohor 8122d 02h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v
37 Link in the header changed. mohor 8135d 08h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).		 mohor 8184d 04h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v
32 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8184d 08h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v

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