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[/] [ethmac/] [tags/] [rel_7/] [rtl/] [verilog/] [eth_defines.v] - Rev 338


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338 root 4893d 02h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v
335 New directory structure. root 4950d 07h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v
228 This commit was manufactured by cvs2svn to create tag 'rel_7'. 7284d 00h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7292d 01h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v
211 Bist added. mohor 7292d 01h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
mohor 7308d 23h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v
145 Defines for control registers added (ETH_TXCTRL and ETH_RXCTRL). mohor 7327d 23h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v
137 Defines for register width added. mii_rst signal in MIIMODER register
mohor 7346d 19h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v
134 Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No
need to multiply or devide any more.
mohor 7348d 22h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7371d 02h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v
106 Outputs registered. Reset changed for eth_wishbone module. mohor 7452d 07h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v
105 Compiler directives added. Tx and Rx fifo size incremented. A "late collision"
bug fixed.
mohor 7461d 09h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
mohor 7497d 05h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v
73 Number of interrupts changed mohor 7518d 01h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v
68 Registered trimmed. Unused registers removed. mohor 7528d 03h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 7528d 04h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v
55 Changed that were lost with last update put back to the file. mohor 7529d 07h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v
52 Modified for Address Checking,
addition of eth_addrcheck.v
billditt 7529d 21h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v
46 HASH0 and HASH1 registers added. mohor 7532d 01h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v
42 Rx status is written back to the BD. mohor 7536d 01h /ethmac/tags/rel_7/rtl/verilog/eth_defines.v

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