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[/] [ethmac/] [tags/] [rel_7/] [rtl/] [verilog/] [eth_top.v] - Rev 95

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Rev Log message Author Age Path
95 md_padoen_o changed to md_padoe_o. Signal was always active high, just
name was incorrect.		 mohor 8075d 12h /ethmac/tags/rel_7/rtl/verilog/eth_top.v
80 Small fixes for external/internal DMA missmatches. mohor 8102d 08h /ethmac/tags/rel_7/rtl/verilog/eth_top.v
76 Interrupts changed in the top file mohor 8102d 09h /ethmac/tags/rel_7/rtl/verilog/eth_top.v
70 Small fixes. mohor 8110d 15h /ethmac/tags/rel_7/rtl/verilog/eth_top.v
68 Registered trimmed. Unused registers removed. mohor 8112d 11h /ethmac/tags/rel_7/rtl/verilog/eth_top.v
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8112d 12h /ethmac/tags/rel_7/rtl/verilog/eth_top.v
65 Testbench fixed, code simplified, unused signals removed. mohor 8112d 18h /ethmac/tags/rel_7/rtl/verilog/eth_top.v
63 RxAbort is connected differently. mohor 8113d 12h /ethmac/tags/rel_7/rtl/verilog/eth_top.v
59 Changes that were lost when updating from 1.11 to 1.14 fixed. mohor 8113d 14h /ethmac/tags/rel_7/rtl/verilog/eth_top.v
52 Modified for Address Checking,
addition of eth_addrcheck.v		 billditt 8114d 05h /ethmac/tags/rel_7/rtl/verilog/eth_top.v
47 HASH0 and HASH1 registers added. Registers address width was
changed to 8 bits.		 mohor 8116d 08h /ethmac/tags/rel_7/rtl/verilog/eth_top.v
43 Tx status is written back to the BD. mohor 8117d 16h /ethmac/tags/rel_7/rtl/verilog/eth_top.v
42 Rx status is written back to the BD. mohor 8120d 09h /ethmac/tags/rel_7/rtl/verilog/eth_top.v
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 8122d 11h /ethmac/tags/rel_7/rtl/verilog/eth_top.v
37 Link in the header changed. mohor 8136d 15h /ethmac/tags/rel_7/rtl/verilog/eth_top.v
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).		 mohor 8185d 10h /ethmac/tags/rel_7/rtl/verilog/eth_top.v
33 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8185d 15h /ethmac/tags/rel_7/rtl/verilog/eth_top.v
23 Number of addresses (wb_adr_i) minimized. mohor 8232d 14h /ethmac/tags/rel_7/rtl/verilog/eth_top.v
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.		 mohor 8232d 17h /ethmac/tags/rel_7/rtl/verilog/eth_top.v
21 Status signals changed, Adress decoding changed, interrupt controller
added.		 mohor 8233d 13h /ethmac/tags/rel_7/rtl/verilog/eth_top.v

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