URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_7/] [rtl/] [verilog/] [eth_wishbone.v] - Rev 164

Rev	Log message	Author	Age	Path
86	Big Endian problem when sending frames fixed.	mohor	8100d 04h	/ethmac/tags/rel_7/rtl/verilog/eth_wishbone.v
82	Byte ordering changed (Big Endian used). casex changed with case because Xilinx Foundation had problems. Tested in HW. It WORKS.	mohor	8105d 16h	/ethmac/tags/rel_7/rtl/verilog/eth_wishbone.v
80	Small fixes for external/internal DMA missmatches.	mohor	8109d 18h	/ethmac/tags/rel_7/rtl/verilog/eth_wishbone.v
77	Interrupts changed	mohor	8109d 19h	/ethmac/tags/rel_7/rtl/verilog/eth_wishbone.v
64	Status was not written correctly when frames were discarted because of address mismatch.	mohor	8120d 18h	/ethmac/tags/rel_7/rtl/verilog/eth_wishbone.v
61	RxStartFrm cleared when abort or retry comes.	mohor	8120d 23h	/ethmac/tags/rel_7/rtl/verilog/eth_wishbone.v
60	Changes that were lost when updating from 1.5 to 1.8 fixed.	mohor	8120d 23h	/ethmac/tags/rel_7/rtl/verilog/eth_wishbone.v
54	Addition of new module eth_addrcheck.v	billditt	8121d 14h	/ethmac/tags/rel_7/rtl/verilog/eth_wishbone.v
48	RxOverRun added to statuses.	mohor	8123d 18h	/ethmac/tags/rel_7/rtl/verilog/eth_wishbone.v
43	Tx status is written back to the BD.	mohor	8125d 02h	/ethmac/tags/rel_7/rtl/verilog/eth_wishbone.v