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236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 7849d 15h /ethmac/tags/rel_9/
235 rev 4. mohor 7850d 06h /ethmac/tags/rel_9/
234 Figure list assed to the revision 3. mohor 7850d 14h /ethmac/tags/rel_9/
233 Revision 0.3 released. Some figures added. mohor 7850d 14h /ethmac/tags/rel_9/
232 fpga define added. mohor 7855d 09h /ethmac/tags/rel_9/
231 Description of Core Modules added (figure). mohor 7857d 11h /ethmac/tags/rel_9/
229 case changed to casex. mohor 7861d 07h /ethmac/tags/rel_9/
227 Changed BIST scan signals. tadejm 7861d 11h /ethmac/tags/rel_9/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7861d 12h /ethmac/tags/rel_9/
225 Some minor changes. tadejm 7861d 13h /ethmac/tags/rel_9/
224 Signals for a wave window in Modelsim. tadejm 7861d 14h /ethmac/tags/rel_9/
223 Some code changed due to bug fixes. tadejm 7861d 14h /ethmac/tags/rel_9/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.		 mohor 7865d 12h /ethmac/tags/rel_9/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.		 mohor 7868d 13h /ethmac/tags/rel_9/
218 Typo error fixed. (When using Bist) mohor 7868d 15h /ethmac/tags/rel_9/
217 Bist supported. mohor 7868d 15h /ethmac/tags/rel_9/
216 Bist signals added. mohor 7868d 15h /ethmac/tags/rel_9/
215 Bist supported. mohor 7868d 15h /ethmac/tags/rel_9/
214 Signals for WISHBONE B3 compliant interface added. mohor 7869d 11h /ethmac/tags/rel_9/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.		 mohor 7869d 11h /ethmac/tags/rel_9/
212 Minor $display change. mohor 7869d 11h /ethmac/tags/rel_9/
211 Bist added. mohor 7869d 12h /ethmac/tags/rel_9/
210 BIST added. mohor 7869d 12h /ethmac/tags/rel_9/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7870d 15h /ethmac/tags/rel_9/
208 Virtual Silicon RAMs moved to lib directory tadej 7886d 09h /ethmac/tags/rel_9/
207 Virtual Silicon RAM support fixed tadej 7886d 09h /ethmac/tags/rel_9/
206 Virtual Silicon RAM added to the simulation. mohor 7886d 09h /ethmac/tags/rel_9/
205 ETH_VIRTUAL_SILICON_RAM supported. mohor 7886d 10h /ethmac/tags/rel_9/
204 ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation). mohor 7886d 10h /ethmac/tags/rel_9/
203 Virtual Silicon RAM might be used in the ASIC implementation of the ethernet
core.		 mohor 7886d 10h /ethmac/tags/rel_9/

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