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Rev Log message Author Age Path
338 root 3723d 03h /ethmac/tags/rel_9/
335 New directory structure. root 3780d 08h /ethmac/tags/rel_9/
237 This commit was manufactured by cvs2svn to create tag 'rel_9'. 6102d 05h /ethmac/tags/rel_9/
236 State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery. mohor 6102d 05h /ethmac/tags/rel_9/
235 rev 4. mohor 6102d 20h /ethmac/tags/rel_9/
234 Figure list assed to the revision 3. mohor 6103d 04h /ethmac/tags/rel_9/
233 Revision 0.3 released. Some figures added. mohor 6103d 04h /ethmac/tags/rel_9/
232 fpga define added. mohor 6107d 23h /ethmac/tags/rel_9/
231 Description of Core Modules added (figure). mohor 6110d 00h /ethmac/tags/rel_9/
229 case changed to casex. mohor 6113d 21h /ethmac/tags/rel_9/
227 Changed BIST scan signals. tadejm 6114d 01h /ethmac/tags/rel_9/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 6114d 02h /ethmac/tags/rel_9/
225 Some minor changes. tadejm 6114d 03h /ethmac/tags/rel_9/
224 Signals for a wave window in Modelsim. tadejm 6114d 04h /ethmac/tags/rel_9/
223 Some code changed due to bug fixes. tadejm 6114d 04h /ethmac/tags/rel_9/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 6118d 02h /ethmac/tags/rel_9/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
finished.
mohor 6121d 02h /ethmac/tags/rel_9/
218 Typo error fixed. (When using Bist) mohor 6121d 04h /ethmac/tags/rel_9/
217 Bist supported. mohor 6121d 04h /ethmac/tags/rel_9/
216 Bist signals added. mohor 6121d 05h /ethmac/tags/rel_9/
215 Bist supported. mohor 6121d 05h /ethmac/tags/rel_9/
214 Signals for WISHBONE B3 compliant interface added. mohor 6122d 01h /ethmac/tags/rel_9/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 6122d 01h /ethmac/tags/rel_9/
212 Minor $display change. mohor 6122d 01h /ethmac/tags/rel_9/
211 Bist added. mohor 6122d 02h /ethmac/tags/rel_9/
210 BIST added. mohor 6122d 02h /ethmac/tags/rel_9/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 6123d 05h /ethmac/tags/rel_9/
208 Virtual Silicon RAMs moved to lib directory tadej 6138d 23h /ethmac/tags/rel_9/
207 Virtual Silicon RAM support fixed tadej 6138d 23h /ethmac/tags/rel_9/
206 Virtual Silicon RAM added to the simulation. mohor 6138d 23h /ethmac/tags/rel_9/

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