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[/] [ethmac/] [tags/] [rel_9/] [rtl/] - Rev 134

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Rev	Log message	Author	Age	Path
134	Register TX_BD_NUM is changed so it contains value of the Tx buffer descriptors. No need to multiply or devide any more.	mohor	7925d 17h	/ethmac/tags/rel_9/rtl
133	- Busy signal was not set on time when scan status operation was performed and clock was divided with more than 2. - Nvalid remains valid two more clocks (was previously cleared too soon).	mohor	7925d 18h	/ethmac/tags/rel_9/rtl
132	LinkFailRegister is reflecting the status of the PHY's link fail status bit.	mohor	7925d 18h	/ethmac/tags/rel_9/rtl
131	LinkFail signal was not latching appropriate bit.	mohor	7925d 18h	/ethmac/tags/rel_9/rtl
129	Traffic cop with 2 wishbone master interfaces and 2 wishbona slave interfaces: - Host connects to the master interface - Ethernet master (DMA) connects to the second master interface - Memory interface connects to the slave interface - Ethernet slave interface (access to registers and BDs) connects to second slave interface	mohor	7925d 19h	/ethmac/tags/rel_9/rtl
127	WriteRxDataToMemory signal changed so end of frame (when last word is written to fifo) is changed.	mohor	7945d 18h	/ethmac/tags/rel_9/rtl
126	InvalidSymbol generation changed.	mohor	7945d 18h	/ethmac/tags/rel_9/rtl
125	RxAbort changed. Packets received with MRxErr (from PHY) are also aborted.	mohor	7945d 18h	/ethmac/tags/rel_9/rtl
122	ethernet spram added. So far a generic ram and xilinx RAMB4 are used.	mohor	7947d 20h	/ethmac/tags/rel_9/rtl
120	Unused files removed.	mohor	7947d 21h	/ethmac/tags/rel_9/rtl
119	Ram , used for BDs changed from generic_spram to eth_spram_256x32.	mohor	7947d 21h	/ethmac/tags/rel_9/rtl
118	ShiftEnded synchronization changed.	mohor	7951d 12h	/ethmac/tags/rel_9/rtl
115	RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.	mohor	7952d 20h	/ethmac/tags/rel_9/rtl
114	EXTERNAL_DMA removed. External DMA not supported.	mohor	7953d 18h	/ethmac/tags/rel_9/rtl
113	RxPointer bug fixed.	mohor	7960d 10h	/ethmac/tags/rel_9/rtl
112	Previous bug wasn't succesfully removed. Now fixed.	mohor	7960d 23h	/ethmac/tags/rel_9/rtl
111	Master state machine had a bug when switching from master write to master read.	mohor	7961d 13h	/ethmac/tags/rel_9/rtl
110	m_wb_cyc_o signal released after every single transfer.	mohor	7961d 16h	/ethmac/tags/rel_9/rtl
109	Comment removed.	mohor	7961d 16h	/ethmac/tags/rel_9/rtl
106	Outputs registered. Reset changed for eth_wishbone module.	mohor	8029d 02h	/ethmac/tags/rel_9/rtl

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[/] [ethmac/] [tags/] [rel_9/] [rtl/] - Rev 134

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