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[/] [ethmac/] [tags/] [rel_9/] [rtl/] [verilog/] - Rev 338

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Rev	Log message	Author	Age	Path
338		root	5494d 19h	/ethmac/tags/rel_9/rtl/verilog
335	New directory structure.	root	5552d 00h	/ethmac/tags/rel_9/rtl/verilog
237	This commit was manufactured by cvs2svn to create tag 'rel_9'.		7873d 21h	/ethmac/tags/rel_9/rtl/verilog
236	State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.	mohor	7873d 21h	/ethmac/tags/rel_9/rtl/verilog
232	fpga define added.	mohor	7879d 15h	/ethmac/tags/rel_9/rtl/verilog
229	case changed to casex.	mohor	7885d 13h	/ethmac/tags/rel_9/rtl/verilog
227	Changed BIST scan signals.	tadejm	7885d 17h	/ethmac/tags/rel_9/rtl/verilog
226	Igor added WB burst support and repaired BUG when handling TX under-run and retry.	tadejm	7885d 18h	/ethmac/tags/rel_9/rtl/verilog
221	TxStatus is written after last access to the TX fifo is finished (in case of abort or retry). TxDone is fixed.	mohor	7889d 18h	/ethmac/tags/rel_9/rtl/verilog
219	txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file, TxDone and TxRetry are generated after the current WISHBONE access is finished.	mohor	7892d 18h	/ethmac/tags/rel_9/rtl/verilog
218	Typo error fixed. (When using Bist)	mohor	7892d 20h	/ethmac/tags/rel_9/rtl/verilog
214	Signals for WISHBONE B3 compliant interface added.	mohor	7893d 17h	/ethmac/tags/rel_9/rtl/verilog
213	Defines changed to have ETH_ prolog. ETH_WISHBONE_B# define added.	mohor	7893d 17h	/ethmac/tags/rel_9/rtl/verilog
212	Minor $display change.	mohor	7893d 17h	/ethmac/tags/rel_9/rtl/verilog
211	Bist added.	mohor	7893d 17h	/ethmac/tags/rel_9/rtl/verilog
210	BIST added.	mohor	7893d 17h	/ethmac/tags/rel_9/rtl/verilog
204	ETH_VIRTUAL_SILICON_RAM supported (for ASIC implementation).	mohor	7910d 15h	/ethmac/tags/rel_9/rtl/verilog
203	Virtual Silicon RAM might be used in the ASIC implementation of the ethernet core.	mohor	7910d 15h	/ethmac/tags/rel_9/rtl/verilog
202	CsMiss added. When address between 0x800 and 0xfff is accessed within Ethernet Core, error acknowledge is generated.	mohor	7913d 17h	/ethmac/tags/rel_9/rtl/verilog
168	CarrierSenseLost bug fixed when operating in full duplex mode.	mohor	7921d 19h	/ethmac/tags/rel_9/rtl/verilog
167	Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.	mohor	7922d 20h	/ethmac/tags/rel_9/rtl/verilog
166	Reception is possible after RxPointer is read and not after BD is read. For that reason RxBDReady is changed to RxReady. Busy_IRQ interrupt connected. When there is no RxBD ready and frame comes, interrupt is generated.	mohor	7923d 20h	/ethmac/tags/rel_9/rtl/verilog
165	HASH improvement needed.	mohor	7923d 23h	/ethmac/tags/rel_9/rtl/verilog
164	Ethernet debug registers removed.	mohor	7923d 23h	/ethmac/tags/rel_9/rtl/verilog
161	Error acknowledge is generated when accessing BDs and RST bit in the MODER register (r_Rst) is set.	mohor	7924d 21h	/ethmac/tags/rel_9/rtl/verilog
160	error acknowledge cycle termination added to display.	mohor	7924d 21h	/ethmac/tags/rel_9/rtl/verilog
159	Async reset for WB_ACK_O removed (when core was in reset, it was impossible to access BDs). RxPointers and TxPointers names changed to be more descriptive. TxUnderRun synchronized.	mohor	7925d 17h	/ethmac/tags/rel_9/rtl/verilog
150	Debug registers reg1, 2, 3, 4 connected. Synchronization of many signals changed (bugs fixed). Access to un-alligned buffers fixed. RxAbort signal was not used OK.	mohor	7929d 15h	/ethmac/tags/rel_9/rtl/verilog
149	Signals related to the control frames connected. Debug registers reg1, 2, 3, 4 connected.	mohor	7929d 15h	/ethmac/tags/rel_9/rtl/verilog
148	Bug when last byte of destination address was not checked fixed.	mohor	7929d 15h	/ethmac/tags/rel_9/rtl/verilog

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[/] [ethmac/] [tags/] [rel_9/] [rtl/] [verilog/] - Rev 338

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