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Rev Log message Author Age Path
368 dbg_dat0 only exist when `DEBUG_WISHBONE is set olof 2833d 05h /ethmac/trunk/
367 Remove Wishbone B3 define. For classic wishbone, these ports can just be ignored olof 2896d 03h /ethmac/trunk/
366 Readded eth_top.v with a deprecation warning olof 3020d 06h /ethmac/trunk/
365 Whitespace cleanup olof 3021d 06h /ethmac/trunk/
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 3022d 03h /ethmac/trunk/
360 Added partial implementation of the debug register from ORPSoC olof 3023d 11h /ethmac/trunk/
359 Verilator linting fixes olof 3025d 13h /ethmac/trunk/
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 3027d 03h /ethmac/trunk/
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 3027d 03h /ethmac/trunk/
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 3027d 05h /ethmac/trunk/
355 Import Julius Baxter's verilator hints from ORPSoC olof 3027d 06h /ethmac/trunk/
354 Whitespace cleanup olof 3027d 06h /ethmac/trunk/
353 Inherit fixes for bit width of constants from ORPSoC olof 3029d 08h /ethmac/trunk/
352 Removed delayed assignments from rtl code olof 3033d 14h /ethmac/trunk/
351 Turn defines into parameters in eth_cop olof 3042d 03h /ethmac/trunk/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 3042d 04h /ethmac/trunk/
349 Make all parameters configurable from top level olof 3043d 05h /ethmac/trunk/
348 Added option to dump VCD files olof 3044d 04h /ethmac/trunk/
347 Added information about running with Icarus Verilog olof 3044d 04h /ethmac/trunk/
346 Updated project location olof 3044d 06h /ethmac/trunk/

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