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Rev Log message Author Age Path
127 WriteRxDataToMemory signal changed so end of frame (when last word is
written to fifo) is changed.
mohor 7994d 05h /ethmac/trunk/
126 InvalidSymbol generation changed. mohor 7994d 05h /ethmac/trunk/
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
mohor 7994d 05h /ethmac/trunk/
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 7994d 06h /ethmac/trunk/
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 7996d 07h /ethmac/trunk/
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 7996d 07h /ethmac/trunk/
120 Unused files removed. mohor 7996d 08h /ethmac/trunk/
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7996d 08h /ethmac/trunk/
118 ShiftEnded synchronization changed. mohor 7999d 23h /ethmac/trunk/
117 Clock mrx_clk set to 2.5 MHz. mohor 8000d 09h /ethmac/trunk/
116 Testing environment also includes traffic cop, memory interface and host
mohor 8000d 09h /ethmac/trunk/
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 8001d 07h /ethmac/trunk/
114 EXTERNAL_DMA removed. External DMA not supported. mohor 8002d 04h /ethmac/trunk/
113 RxPointer bug fixed. mohor 8008d 20h /ethmac/trunk/
112 Previous bug wasn't succesfully removed. Now fixed. mohor 8009d 10h /ethmac/trunk/
111 Master state machine had a bug when switching from master write to
master read.
mohor 8009d 23h /ethmac/trunk/
110 m_wb_cyc_o signal released after every single transfer. mohor 8010d 02h /ethmac/trunk/
109 Comment removed. mohor 8010d 03h /ethmac/trunk/
108 Testbench supports unaligned accesses. mohor 8077d 13h /ethmac/trunk/
107 TX_BUF_BASE changed. mohor 8077d 13h /ethmac/trunk/

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