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Rev Log message Author Age Path
229 case changed to casex. mohor 7800d 17h /ethmac/trunk/
227 Changed BIST scan signals. tadejm 7800d 21h /ethmac/trunk/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7800d 23h /ethmac/trunk/
225 Some minor changes. tadejm 7800d 23h /ethmac/trunk/
224 Signals for a wave window in Modelsim. tadejm 7801d 00h /ethmac/trunk/
223 Some code changed due to bug fixes. tadejm 7801d 00h /ethmac/trunk/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7804d 22h /ethmac/trunk/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
mohor 7807d 23h /ethmac/trunk/
218 Typo error fixed. (When using Bist) mohor 7808d 01h /ethmac/trunk/
217 Bist supported. mohor 7808d 01h /ethmac/trunk/
216 Bist signals added. mohor 7808d 01h /ethmac/trunk/
215 Bist supported. mohor 7808d 02h /ethmac/trunk/
214 Signals for WISHBONE B3 compliant interface added. mohor 7808d 21h /ethmac/trunk/
213 Defines changed to have ETH_ prolog.
ETH_WISHBONE_B# define added.
mohor 7808d 21h /ethmac/trunk/
212 Minor $display change. mohor 7808d 22h /ethmac/trunk/
211 Bist added. mohor 7808d 22h /ethmac/trunk/
210 BIST added. mohor 7808d 22h /ethmac/trunk/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 7810d 01h /ethmac/trunk/
208 Virtual Silicon RAMs moved to lib directory tadej 7825d 19h /ethmac/trunk/
207 Virtual Silicon RAM support fixed tadej 7825d 19h /ethmac/trunk/

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