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Rev Log message Author Age Path
232 fpga define added. mohor 7889d 04h /ethmac/trunk/
231 Description of Core Modules added (figure). mohor 7891d 05h /ethmac/trunk/
229 case changed to casex. mohor 7895d 02h /ethmac/trunk/
227 Changed BIST scan signals. tadejm 7895d 05h /ethmac/trunk/
226 Igor added WB burst support and repaired BUG when handling TX under-run and retry. tadejm 7895d 07h /ethmac/trunk/
225 Some minor changes. tadejm 7895d 07h /ethmac/trunk/
224 Signals for a wave window in Modelsim. tadejm 7895d 08h /ethmac/trunk/
223 Some code changed due to bug fixes. tadejm 7895d 09h /ethmac/trunk/
221 TxStatus is written after last access to the TX fifo is finished (in case of abort
or retry). TxDone is fixed.
mohor 7899d 06h /ethmac/trunk/
219 txfifo_cnt and rxfifo_cnt counters width is defined in the eth_define.v file,
TxDone and TxRetry are generated after the current WISHBONE access is
mohor 7902d 07h /ethmac/trunk/

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