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Rev Log message Author Age Path
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 3410d 20h /ethmac/trunk/
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 3410d 21h /ethmac/trunk/
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 3410d 22h /ethmac/trunk/
355 Import Julius Baxter's verilator hints from ORPSoC olof 3410d 23h /ethmac/trunk/
354 Whitespace cleanup olof 3411d 00h /ethmac/trunk/
353 Inherit fixes for bit width of constants from ORPSoC olof 3413d 01h /ethmac/trunk/
352 Removed delayed assignments from rtl code olof 3417d 07h /ethmac/trunk/
351 Turn defines into parameters in eth_cop olof 3425d 21h /ethmac/trunk/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 3425d 21h /ethmac/trunk/
349 Make all parameters configurable from top level olof 3426d 22h /ethmac/trunk/
348 Added option to dump VCD files olof 3427d 21h /ethmac/trunk/
347 Added information about running with Icarus Verilog olof 3427d 22h /ethmac/trunk/
346 Updated project location olof 3428d 00h /ethmac/trunk/
345 Temporarily disable failing tests olof 3428d 01h /ethmac/trunk/
344 bit 9 in phy control register is self clearing olof 3434d 03h /ethmac/trunk/
343 Address miss should not be asserted on short frames olof 3437d 23h /ethmac/trunk/
342 Added cast to avoid inequality when comparing different data types olof 3437d 23h /ethmac/trunk/
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 3438d 00h /ethmac/trunk/
340 Don't fail if log dir already exists olof 3438d 21h /ethmac/trunk/
339 Added basic support for Icarus Verilog olof 3439d 20h /ethmac/trunk/

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