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Rev Log message Author Age Path
360 Added partial implementation of the debug register from ORPSoC olof 4722d 21h /ethmac/trunk/
359 Verilator linting fixes olof 4724d 23h /ethmac/trunk/
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4726d 13h /ethmac/trunk/
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4726d 13h /ethmac/trunk/
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4726d 15h /ethmac/trunk/
355 Import Julius Baxter's verilator hints from ORPSoC olof 4726d 16h /ethmac/trunk/
354 Whitespace cleanup olof 4726d 16h /ethmac/trunk/
353 Inherit fixes for bit width of constants from ORPSoC olof 4728d 18h /ethmac/trunk/
352 Removed delayed assignments from rtl code olof 4733d 00h /ethmac/trunk/
351 Turn defines into parameters in eth_cop olof 4741d 14h /ethmac/trunk/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4741d 14h /ethmac/trunk/
349 Make all parameters configurable from top level olof 4742d 15h /ethmac/trunk/
348 Added option to dump VCD files olof 4743d 14h /ethmac/trunk/
347 Added information about running with Icarus Verilog olof 4743d 15h /ethmac/trunk/
346 Updated project location olof 4743d 17h /ethmac/trunk/
345 Temporarily disable failing tests olof 4743d 18h /ethmac/trunk/
344 bit 9 in phy control register is self clearing olof 4749d 20h /ethmac/trunk/
343 Address miss should not be asserted on short frames olof 4753d 16h /ethmac/trunk/
342 Added cast to avoid inequality when comparing different data types olof 4753d 16h /ethmac/trunk/
341 Reset AdressMiss signal on new frames to prevent reporting the old status if new frame is short olof 4753d 17h /ethmac/trunk/

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