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Rev Log message Author Age Path
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 3362d 06h /ethmac/trunk/
360 Added partial implementation of the debug register from ORPSoC olof 3363d 13h /ethmac/trunk/
359 Verilator linting fixes olof 3365d 16h /ethmac/trunk/
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 3367d 06h /ethmac/trunk/
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 3367d 06h /ethmac/trunk/
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 3367d 08h /ethmac/trunk/
355 Import Julius Baxter's verilator hints from ORPSoC olof 3367d 08h /ethmac/trunk/
354 Whitespace cleanup olof 3367d 09h /ethmac/trunk/
353 Inherit fixes for bit width of constants from ORPSoC olof 3369d 10h /ethmac/trunk/
352 Removed delayed assignments from rtl code olof 3373d 16h /ethmac/trunk/
351 Turn defines into parameters in eth_cop olof 3382d 06h /ethmac/trunk/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 3382d 07h /ethmac/trunk/
349 Make all parameters configurable from top level olof 3383d 07h /ethmac/trunk/
348 Added option to dump VCD files olof 3384d 06h /ethmac/trunk/
347 Added information about running with Icarus Verilog olof 3384d 07h /ethmac/trunk/
346 Updated project location olof 3384d 09h /ethmac/trunk/
345 Temporarily disable failing tests olof 3384d 11h /ethmac/trunk/
344 bit 9 in phy control register is self clearing olof 3390d 13h /ethmac/trunk/
343 Address miss should not be asserted on short frames olof 3394d 09h /ethmac/trunk/
342 Added cast to avoid inequality when comparing different data types olof 3394d 09h /ethmac/trunk/

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