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Rev Log message Author Age Path
366 Readded eth_top.v with a deprecation warning olof 4196d 12h /ethmac/trunk/
365 Whitespace cleanup olof 4197d 11h /ethmac/trunk/
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 4198d 08h /ethmac/trunk/
360 Added partial implementation of the debug register from ORPSoC olof 4199d 16h /ethmac/trunk/
359 Verilator linting fixes olof 4201d 18h /ethmac/trunk/
358 Rename do to dato to avoid conflict with SystemVerilog (inherited from Julius Baxter's ORPSoC version olof 4203d 08h /ethmac/trunk/
357 Bit width, assignment and white space fixes by Julius Baxter, inherited from ORPSoC olof 4203d 09h /ethmac/trunk/
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4203d 10h /ethmac/trunk/
355 Import Julius Baxter's verilator hints from ORPSoC olof 4203d 11h /ethmac/trunk/
354 Whitespace cleanup olof 4203d 11h /ethmac/trunk/
353 Inherit fixes for bit width of constants from ORPSoC olof 4205d 13h /ethmac/trunk/
352 Removed delayed assignments from rtl code olof 4209d 19h /ethmac/trunk/
351 Turn defines into parameters in eth_cop olof 4218d 09h /ethmac/trunk/
350 Turn M[1-2]_ADDRESSED_S[1-2] defines into wires olof 4218d 09h /ethmac/trunk/
349 Make all parameters configurable from top level olof 4219d 10h /ethmac/trunk/
348 Added option to dump VCD files olof 4220d 09h /ethmac/trunk/
347 Added information about running with Icarus Verilog olof 4220d 10h /ethmac/trunk/
346 Updated project location olof 4220d 12h /ethmac/trunk/
345 Temporarily disable failing tests olof 4220d 13h /ethmac/trunk/
344 bit 9 in phy control register is self clearing olof 4226d 15h /ethmac/trunk/

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