URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

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[/] [ethmac/] [trunk/] - Rev 45

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Rev	Log message	Author	Age	Path
45	Ethernet Datasheet added.	mohor	8121d 02h	/ethmac/trunk/
44	Ethernet Datasheet added to cvs.	mohor	8121d 02h	/ethmac/trunk/
43	Tx status is written back to the BD.	mohor	8122d 04h	/ethmac/trunk/
42	Rx status is written back to the BD.	mohor	8124d 20h	/ethmac/trunk/
41	non-DMA host interface added. Select the right configutation in eth_defines.	mohor	8126d 23h	/ethmac/trunk/
40	Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200 MHz. Statuses, overrun, control frame transmission and reception still need to be fixed.	mohor	8127d 20h	/ethmac/trunk/
39	Tx part finished. TxStatus needs to be fixed. Pause request needs to be added.	mohor	8132d 00h	/ethmac/trunk/
38	Initial version. Equals to eth_wishbonedma.v at this moment.	mohor	8141d 02h	/ethmac/trunk/
37	Link in the header changed.	mohor	8141d 02h	/ethmac/trunk/
36	TX_BD_NUM register added instead of the RB_BD_ADDR.	mohor	8187d 00h	/ethmac/trunk/
35	RX_BD_NUM changed to TX_BD_NUM. Few typos corrected.	mohor	8189d 22h	/ethmac/trunk/
34	RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors instead of the number of RX descriptors).	mohor	8189d 22h	/ethmac/trunk/
33	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8190d 02h	/ethmac/trunk/
32	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8190d 02h	/ethmac/trunk/
31	RX_BD_NUM register added instead of the RB_BD_ADDR.	mohor	8190d 03h	/ethmac/trunk/
30	BD section updated.	mohor	8192d 00h	/ethmac/trunk/
29	Generic memory model is used. Defines are changed for the same reason.	mohor	8211d 22h	/ethmac/trunk/
28	New release. Name changed to lower case.	mohor	8214d 14h	/ethmac/trunk/
27	File names changed to lower case.	mohor	8214d 14h	/ethmac/trunk/
26	First release of product brief.	mohor	8214d 14h	/ethmac/trunk/
25	First release of product brief.	mohor	8214d 14h	/ethmac/trunk/
24	Log file added.	mohor	8237d 01h	/ethmac/trunk/
23	Number of addresses (wb_adr_i) minimized.	mohor	8237d 01h	/ethmac/trunk/
22	eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project.	mohor	8237d 04h	/ethmac/trunk/
21	Status signals changed, Adress decoding changed, interrupt controller added.	mohor	8238d 01h	/ethmac/trunk/
20	Defines changed (All precede with ETH_). Small changes because some tools generate warnings when two operands are together. Synchronization between two clocks domains in eth_wishbonedma.v is changed (due to ASIC demands).	mohor	8261d 22h	/ethmac/trunk/
19	Defines changed (All precede with ETH_). Small changes because some tools generate warnings when two operands are together. Synchronization between two clocks domains in eth_wishbonedma.v is changed (due to ASIC demands).	mohor	8261d 22h	/ethmac/trunk/
18	Few little NCSIM warnings fixed.	mohor	8274d 23h	/ethmac/trunk/
17	Signal names changed on the top level for easier pad insertion (ASIC).	mohor	8301d 23h	/ethmac/trunk/
16	"else" was missing within the always block in file eth_wishbonedma.v.	mohor	8309d 04h	/ethmac/trunk/

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[/] [ethmac/] [trunk/] - Rev 45

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