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[/] [ethmac/] [trunk/] [bench/] [verilog/] - Rev 189

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189 Simple testbench that includes eth_cop, eth_host and eth_memory modules.
This testbench is used for testing the whole environment. Use tb_ethernet
testbench for testing just the ethernet MAC core (many tests).
mohor 7946d 20h /ethmac/trunk/bench/verilog/
188 PHY changed. tadej 7947d 16h /ethmac/trunk/bench/verilog/
182 Full duplex test improved. tadej 7948d 18h /ethmac/trunk/bench/verilog/
181 MIIM test look better. mohor 7948d 21h /ethmac/trunk/bench/verilog/
180 Bench outputs data to display every 128 bytes. mohor 7951d 17h /ethmac/trunk/bench/verilog/
179 Beautiful tests merget together mohor 7951d 18h /ethmac/trunk/bench/verilog/
178 Rearanged testcases mohor 7951d 18h /ethmac/trunk/bench/verilog/
177 Bug in MIIM fixed. mohor 7951d 22h /ethmac/trunk/bench/verilog/
170 Headers changed. mohor 7952d 00h /ethmac/trunk/bench/verilog/
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 7952d 00h /ethmac/trunk/bench/verilog/
158 Typo fixed. mohor 7956d 20h /ethmac/trunk/bench/verilog/
157 This testbench will soon be obsolete. Please use tb_ethernet.v mohor 7959d 01h /ethmac/trunk/bench/verilog/
156 Valid testbench. mohor 7959d 01h /ethmac/trunk/bench/verilog/
155 Minor changes. mohor 7959d 01h /ethmac/trunk/bench/verilog/
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 8001d 19h /ethmac/trunk/bench/verilog/
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 8003d 20h /ethmac/trunk/bench/verilog/
117 Clock mrx_clk set to 2.5 MHz. mohor 8007d 22h /ethmac/trunk/bench/verilog/
116 Testing environment also includes traffic cop, memory interface and host
interface.
mohor 8007d 22h /ethmac/trunk/bench/verilog/
108 Testbench supports unaligned accesses. mohor 8085d 02h /ethmac/trunk/bench/verilog/
107 TX_BUF_BASE changed. mohor 8085d 02h /ethmac/trunk/bench/verilog/

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