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[/] [ethmac/] [trunk/] [bench/] [verilog/] - Rev 189

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189 Simple testbench that includes eth_cop, eth_host and eth_memory modules.
This testbench is used for testing the whole environment. Use tb_ethernet
testbench for testing just the ethernet MAC core (many tests).		 mohor 7900d 16h /ethmac/trunk/bench/verilog/
188 PHY changed. tadej 7901d 13h /ethmac/trunk/bench/verilog/
182 Full duplex test improved. tadej 7902d 15h /ethmac/trunk/bench/verilog/
181 MIIM test look better. mohor 7902d 18h /ethmac/trunk/bench/verilog/
180 Bench outputs data to display every 128 bytes. mohor 7905d 14h /ethmac/trunk/bench/verilog/
179 Beautiful tests merget together mohor 7905d 14h /ethmac/trunk/bench/verilog/
178 Rearanged testcases mohor 7905d 14h /ethmac/trunk/bench/verilog/
177 Bug in MIIM fixed. mohor 7905d 18h /ethmac/trunk/bench/verilog/
170 Headers changed. mohor 7905d 20h /ethmac/trunk/bench/verilog/
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 7905d 21h /ethmac/trunk/bench/verilog/
158 Typo fixed. mohor 7910d 17h /ethmac/trunk/bench/verilog/
157 This testbench will soon be obsolete. Please use tb_ethernet.v mohor 7912d 22h /ethmac/trunk/bench/verilog/
156 Valid testbench. mohor 7912d 22h /ethmac/trunk/bench/verilog/
155 Minor changes. mohor 7912d 22h /ethmac/trunk/bench/verilog/
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 7955d 16h /ethmac/trunk/bench/verilog/
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 7957d 16h /ethmac/trunk/bench/verilog/
117 Clock mrx_clk set to 2.5 MHz. mohor 7961d 19h /ethmac/trunk/bench/verilog/
116 Testing environment also includes traffic cop, memory interface and host
interface.		 mohor 7961d 19h /ethmac/trunk/bench/verilog/
108 Testbench supports unaligned accesses. mohor 8038d 22h /ethmac/trunk/bench/verilog/
107 TX_BUF_BASE changed. mohor 8038d 23h /ethmac/trunk/bench/verilog/
92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.		 mohor 8083d 20h /ethmac/trunk/bench/verilog/
80 Small fixes for external/internal DMA missmatches. mohor 8104d 16h /ethmac/trunk/bench/verilog/
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8114d 20h /ethmac/trunk/bench/verilog/
66 Testbench fixed, code simplified, unused signals removed. mohor 8115d 02h /ethmac/trunk/bench/verilog/
51 Added separate tests for Multicast, Unicast, Broadcast billditt 8116d 13h /ethmac/trunk/bench/verilog/
49 HASH0 and HASH1 register read/write added. mohor 8118d 12h /ethmac/trunk/bench/verilog/
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 8124d 19h /ethmac/trunk/bench/verilog/
36 TX_BD_NUM register added instead of the RB_BD_ADDR. mohor 8184d 20h /ethmac/trunk/bench/verilog/
23 Number of addresses (wb_adr_i) minimized. mohor 8234d 21h /ethmac/trunk/bench/verilog/
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.		 mohor 8235d 00h /ethmac/trunk/bench/verilog/

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