OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [bench/] [verilog/] - Rev 260

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.
mohor 7877d 16h /ethmac/trunk/bench/verilog/
254 Temp version. mohor 7879d 10h /ethmac/trunk/bench/verilog/
252 Just some updates. tadejm 7879d 12h /ethmac/trunk/bench/verilog/
243 Late collision is not reported any more. tadejm 7884d 17h /ethmac/trunk/bench/verilog/
227 Changed BIST scan signals. tadejm 7911d 13h /ethmac/trunk/bench/verilog/
223 Some code changed due to bug fixes. tadejm 7911d 16h /ethmac/trunk/bench/verilog/
216 Bist signals added. mohor 7918d 17h /ethmac/trunk/bench/verilog/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 7920d 17h /ethmac/trunk/bench/verilog/
194 Full duplex tests modified and testbench bug repaired. tadej 7939d 16h /ethmac/trunk/bench/verilog/
192 Some additional reports added tadej 7941d 12h /ethmac/trunk/bench/verilog/
191 Bug repaired in eth_phy device tadej 7941d 12h /ethmac/trunk/bench/verilog/
189 Simple testbench that includes eth_cop, eth_host and eth_memory modules.
This testbench is used for testing the whole environment. Use tb_ethernet
testbench for testing just the ethernet MAC core (many tests).
mohor 7941d 13h /ethmac/trunk/bench/verilog/
188 PHY changed. tadej 7942d 10h /ethmac/trunk/bench/verilog/
182 Full duplex test improved. tadej 7943d 12h /ethmac/trunk/bench/verilog/
181 MIIM test look better. mohor 7943d 15h /ethmac/trunk/bench/verilog/
180 Bench outputs data to display every 128 bytes. mohor 7946d 11h /ethmac/trunk/bench/verilog/
179 Beautiful tests merget together mohor 7946d 11h /ethmac/trunk/bench/verilog/
178 Rearanged testcases mohor 7946d 11h /ethmac/trunk/bench/verilog/
177 Bug in MIIM fixed. mohor 7946d 15h /ethmac/trunk/bench/verilog/
170 Headers changed. mohor 7946d 18h /ethmac/trunk/bench/verilog/
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 7946d 18h /ethmac/trunk/bench/verilog/
158 Typo fixed. mohor 7951d 14h /ethmac/trunk/bench/verilog/
157 This testbench will soon be obsolete. Please use tb_ethernet.v mohor 7953d 19h /ethmac/trunk/bench/verilog/
156 Valid testbench. mohor 7953d 19h /ethmac/trunk/bench/verilog/
155 Minor changes. mohor 7953d 19h /ethmac/trunk/bench/verilog/
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 7996d 13h /ethmac/trunk/bench/verilog/
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 7998d 13h /ethmac/trunk/bench/verilog/
117 Clock mrx_clk set to 2.5 MHz. mohor 8002d 16h /ethmac/trunk/bench/verilog/
116 Testing environment also includes traffic cop, memory interface and host
interface.
mohor 8002d 16h /ethmac/trunk/bench/verilog/
108 Testbench supports unaligned accesses. mohor 8079d 20h /ethmac/trunk/bench/verilog/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.