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[/] [ethmac/] [trunk/] [bench/] [verilog/] - Rev 263

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263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.
mohor 7849d 13h /ethmac/trunk/bench/verilog/
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.
mohor 7850d 01h /ethmac/trunk/bench/verilog/
254 Temp version. mohor 7851d 19h /ethmac/trunk/bench/verilog/
252 Just some updates. tadejm 7851d 21h /ethmac/trunk/bench/verilog/
243 Late collision is not reported any more. tadejm 7857d 02h /ethmac/trunk/bench/verilog/
227 Changed BIST scan signals. tadejm 7883d 22h /ethmac/trunk/bench/verilog/
223 Some code changed due to bug fixes. tadejm 7884d 01h /ethmac/trunk/bench/verilog/
216 Bist signals added. mohor 7891d 02h /ethmac/trunk/bench/verilog/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 7893d 02h /ethmac/trunk/bench/verilog/
194 Full duplex tests modified and testbench bug repaired. tadej 7912d 01h /ethmac/trunk/bench/verilog/
192 Some additional reports added tadej 7913d 21h /ethmac/trunk/bench/verilog/
191 Bug repaired in eth_phy device tadej 7913d 21h /ethmac/trunk/bench/verilog/
189 Simple testbench that includes eth_cop, eth_host and eth_memory modules.
This testbench is used for testing the whole environment. Use tb_ethernet
testbench for testing just the ethernet MAC core (many tests).
mohor 7913d 22h /ethmac/trunk/bench/verilog/
188 PHY changed. tadej 7914d 19h /ethmac/trunk/bench/verilog/
182 Full duplex test improved. tadej 7915d 21h /ethmac/trunk/bench/verilog/
181 MIIM test look better. mohor 7916d 00h /ethmac/trunk/bench/verilog/
180 Bench outputs data to display every 128 bytes. mohor 7918d 20h /ethmac/trunk/bench/verilog/
179 Beautiful tests merget together mohor 7918d 20h /ethmac/trunk/bench/verilog/
178 Rearanged testcases mohor 7918d 20h /ethmac/trunk/bench/verilog/
177 Bug in MIIM fixed. mohor 7919d 00h /ethmac/trunk/bench/verilog/

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