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[/] [ethmac/] [trunk/] [bench/] [verilog/] - Rev 263

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263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.		 mohor 8243d 14h /ethmac/trunk/bench/verilog/
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.		 mohor 8244d 02h /ethmac/trunk/bench/verilog/
254 Temp version. mohor 8245d 20h /ethmac/trunk/bench/verilog/
252 Just some updates. tadejm 8245d 23h /ethmac/trunk/bench/verilog/
243 Late collision is not reported any more. tadejm 8251d 03h /ethmac/trunk/bench/verilog/
227 Changed BIST scan signals. tadejm 8277d 23h /ethmac/trunk/bench/verilog/
223 Some code changed due to bug fixes. tadejm 8278d 02h /ethmac/trunk/bench/verilog/
216 Bist signals added. mohor 8285d 03h /ethmac/trunk/bench/verilog/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 8287d 03h /ethmac/trunk/bench/verilog/
194 Full duplex tests modified and testbench bug repaired. tadej 8306d 02h /ethmac/trunk/bench/verilog/
192 Some additional reports added tadej 8307d 22h /ethmac/trunk/bench/verilog/
191 Bug repaired in eth_phy device tadej 8307d 22h /ethmac/trunk/bench/verilog/
189 Simple testbench that includes eth_cop, eth_host and eth_memory modules.
This testbench is used for testing the whole environment. Use tb_ethernet
testbench for testing just the ethernet MAC core (many tests).		 mohor 8308d 00h /ethmac/trunk/bench/verilog/
188 PHY changed. tadej 8308d 20h /ethmac/trunk/bench/verilog/
182 Full duplex test improved. tadej 8309d 22h /ethmac/trunk/bench/verilog/
181 MIIM test look better. mohor 8310d 01h /ethmac/trunk/bench/verilog/
180 Bench outputs data to display every 128 bytes. mohor 8312d 21h /ethmac/trunk/bench/verilog/
179 Beautiful tests merget together mohor 8312d 22h /ethmac/trunk/bench/verilog/
178 Rearanged testcases mohor 8312d 22h /ethmac/trunk/bench/verilog/
177 Bug in MIIM fixed. mohor 8313d 02h /ethmac/trunk/bench/verilog/
170 Headers changed. mohor 8313d 04h /ethmac/trunk/bench/verilog/
169 New testbench. Thanks to Tadej M - "The Spammer". mohor 8313d 04h /ethmac/trunk/bench/verilog/
158 Typo fixed. mohor 8318d 00h /ethmac/trunk/bench/verilog/
157 This testbench will soon be obsolete. Please use tb_ethernet.v mohor 8320d 05h /ethmac/trunk/bench/verilog/
156 Valid testbench. mohor 8320d 05h /ethmac/trunk/bench/verilog/
155 Minor changes. mohor 8320d 05h /ethmac/trunk/bench/verilog/
124 Define ETH_MIIMODER_RST corrected to 0x00000400. mohor 8362d 23h /ethmac/trunk/bench/verilog/
121 gsr added for use when ETH_XILINX_RAMB4 define is set. mohor 8365d 00h /ethmac/trunk/bench/verilog/
117 Clock mrx_clk set to 2.5 MHz. mohor 8369d 02h /ethmac/trunk/bench/verilog/
116 Testing environment also includes traffic cop, memory interface and host
interface.		 mohor 8369d 02h /ethmac/trunk/bench/verilog/

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