OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [bench/] [verilog/] - Rev 315

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
315 Updated testbench. Some more testcases, some repaired. tadejm 7470d 23h /ethmac/trunk/bench/verilog
302 mbist signals updated according to newest convention markom 7520d 04h /ethmac/trunk/bench/verilog
299 Artisan RAMs added. mohor 7578d 00h /ethmac/trunk/bench/verilog
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.		 mohor 7646d 00h /ethmac/trunk/bench/verilog
281 Tests test_mac_full_duplex_receive 4-7 fixed to proper BD. mohor 7778d 20h /ethmac/trunk/bench/verilog
279 Underrun test fixed. Many other tests fixed. mohor 7779d 22h /ethmac/trunk/bench/verilog
274 Backup version. Not fully working. tadejm 7787d 16h /ethmac/trunk/bench/verilog
267 Full duplex control frames tested. mohor 7843d 20h /ethmac/trunk/bench/verilog
266 Flow control test almost finished. mohor 7848d 18h /ethmac/trunk/bench/verilog
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.		 mohor 7849d 10h /ethmac/trunk/bench/verilog
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.		 mohor 7849d 22h /ethmac/trunk/bench/verilog
254 Temp version. mohor 7851d 16h /ethmac/trunk/bench/verilog
252 Just some updates. tadejm 7851d 18h /ethmac/trunk/bench/verilog
243 Late collision is not reported any more. tadejm 7856d 23h /ethmac/trunk/bench/verilog
227 Changed BIST scan signals. tadejm 7883d 19h /ethmac/trunk/bench/verilog
223 Some code changed due to bug fixes. tadejm 7883d 22h /ethmac/trunk/bench/verilog
216 Bist signals added. mohor 7890d 22h /ethmac/trunk/bench/verilog
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7892d 23h /ethmac/trunk/bench/verilog
194 Full duplex tests modified and testbench bug repaired. tadej 7911d 21h /ethmac/trunk/bench/verilog
192 Some additional reports added tadej 7913d 18h /ethmac/trunk/bench/verilog
191 Bug repaired in eth_phy device tadej 7913d 18h /ethmac/trunk/bench/verilog
189 Simple testbench that includes eth_cop, eth_host and eth_memory modules.
This testbench is used for testing the whole environment. Use tb_ethernet
testbench for testing just the ethernet MAC core (many tests).		 mohor 7913d 19h /ethmac/trunk/bench/verilog
188 PHY changed. tadej 7914d 16h /ethmac/trunk/bench/verilog
182 Full duplex test improved. tadej 7915d 18h /ethmac/trunk/bench/verilog
181 MIIM test look better. mohor 7915d 21h /ethmac/trunk/bench/verilog
180 Bench outputs data to display every 128 bytes. mohor 7918d 17h /ethmac/trunk/bench/verilog
179 Beautiful tests merget together mohor 7918d 17h /ethmac/trunk/bench/verilog
178 Rearanged testcases mohor 7918d 17h /ethmac/trunk/bench/verilog
177 Bug in MIIM fixed. mohor 7918d 21h /ethmac/trunk/bench/verilog
170 Headers changed. mohor 7918d 23h /ethmac/trunk/bench/verilog

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.