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[/] [ethmac/] [trunk/] [bench/] [verilog/] - Rev 338

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Rev Log message Author Age Path
338 root 5561d 12h /ethmac/trunk/bench/verilog/
335 New directory structure. root 5618d 17h /ethmac/trunk/bench/verilog/
334 Minor fixes for Icarus simulator. igorm 7066d 19h /ethmac/trunk/bench/verilog/
331 Tests for delayed CRC and defer indication added. igorm 7095d 14h /ethmac/trunk/bench/verilog/
318 Latest Ethernet IP core testbench. tadejm 7427d 11h /ethmac/trunk/bench/verilog/
315 Updated testbench. Some more testcases, some repaired. tadejm 7539d 14h /ethmac/trunk/bench/verilog/
302 mbist signals updated according to newest convention markom 7588d 19h /ethmac/trunk/bench/verilog/
299 Artisan RAMs added. mohor 7646d 15h /ethmac/trunk/bench/verilog/
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.		 mohor 7714d 15h /ethmac/trunk/bench/verilog/
281 Tests test_mac_full_duplex_receive 4-7 fixed to proper BD. mohor 7847d 11h /ethmac/trunk/bench/verilog/
279 Underrun test fixed. Many other tests fixed. mohor 7848d 13h /ethmac/trunk/bench/verilog/
274 Backup version. Not fully working. tadejm 7856d 07h /ethmac/trunk/bench/verilog/
267 Full duplex control frames tested. mohor 7912d 11h /ethmac/trunk/bench/verilog/
266 Flow control test almost finished. mohor 7917d 10h /ethmac/trunk/bench/verilog/
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.		 mohor 7918d 01h /ethmac/trunk/bench/verilog/
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.		 mohor 7918d 13h /ethmac/trunk/bench/verilog/
254 Temp version. mohor 7920d 07h /ethmac/trunk/bench/verilog/
252 Just some updates. tadejm 7920d 09h /ethmac/trunk/bench/verilog/
243 Late collision is not reported any more. tadejm 7925d 14h /ethmac/trunk/bench/verilog/
227 Changed BIST scan signals. tadejm 7952d 10h /ethmac/trunk/bench/verilog/

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