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[/] [ethmac/] [trunk/] [bench/] [verilog/] - Rev 338

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Rev	Log message	Author	Age	Path
338		root	5483d 00h	/ethmac/trunk/bench/verilog
335	New directory structure.	root	5540d 05h	/ethmac/trunk/bench/verilog
334	Minor fixes for Icarus simulator.	igorm	6988d 08h	/ethmac/trunk/bench/verilog
331	Tests for delayed CRC and defer indication added.	igorm	7017d 02h	/ethmac/trunk/bench/verilog
318	Latest Ethernet IP core testbench.	tadejm	7348d 23h	/ethmac/trunk/bench/verilog
315	Updated testbench. Some more testcases, some repaired.	tadejm	7461d 03h	/ethmac/trunk/bench/verilog
302	mbist signals updated according to newest convention	markom	7510d 08h	/ethmac/trunk/bench/verilog
299	Artisan RAMs added.	mohor	7568d 03h	/ethmac/trunk/bench/verilog
286	Define file in eth_cop.v is changed to eth_defines.v. Some defines were moved from tb_eth_defines.v to eth_defines.v.	mohor	7636d 04h	/ethmac/trunk/bench/verilog
281	Tests test_mac_full_duplex_receive 4-7 fixed to proper BD.	mohor	7769d 00h	/ethmac/trunk/bench/verilog
279	Underrun test fixed. Many other tests fixed.	mohor	7770d 02h	/ethmac/trunk/bench/verilog
274	Backup version. Not fully working.	tadejm	7777d 20h	/ethmac/trunk/bench/verilog
267	Full duplex control frames tested.	mohor	7833d 23h	/ethmac/trunk/bench/verilog
266	Flow control test almost finished.	mohor	7838d 22h	/ethmac/trunk/bench/verilog
263	test_mac_full_duplex_flow_control tests pretty much finished. TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 10Mbps ) finished. TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED OFF AT ONE RX BD ( 10Mbps ) finished.	mohor	7839d 13h	/ethmac/trunk/bench/verilog
260	test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame finished.	mohor	7840d 02h	/ethmac/trunk/bench/verilog
254	Temp version.	mohor	7841d 19h	/ethmac/trunk/bench/verilog
252	Just some updates.	tadejm	7841d 22h	/ethmac/trunk/bench/verilog
243	Late collision is not reported any more.	tadejm	7847d 02h	/ethmac/trunk/bench/verilog
227	Changed BIST scan signals.	tadejm	7873d 22h	/ethmac/trunk/bench/verilog
223	Some code changed due to bug fixes.	tadejm	7874d 02h	/ethmac/trunk/bench/verilog
216	Bist signals added.	mohor	7881d 02h	/ethmac/trunk/bench/verilog
209	Just back-up; not completed testbench and some testcases are not wotking properly yet.	tadejm	7883d 02h	/ethmac/trunk/bench/verilog
194	Full duplex tests modified and testbench bug repaired.	tadej	7902d 01h	/ethmac/trunk/bench/verilog
192	Some additional reports added	tadej	7903d 22h	/ethmac/trunk/bench/verilog
191	Bug repaired in eth_phy device	tadej	7903d 22h	/ethmac/trunk/bench/verilog
189	Simple testbench that includes eth_cop, eth_host and eth_memory modules. This testbench is used for testing the whole environment. Use tb_ethernet testbench for testing just the ethernet MAC core (many tests).	mohor	7903d 23h	/ethmac/trunk/bench/verilog
188	PHY changed.	tadej	7904d 19h	/ethmac/trunk/bench/verilog
182	Full duplex test improved.	tadej	7905d 22h	/ethmac/trunk/bench/verilog
181	MIIM test look better.	mohor	7906d 00h	/ethmac/trunk/bench/verilog

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[/] [ethmac/] [trunk/] [bench/] [verilog/] - Rev 338

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