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[/] [ethmac/] [trunk/] [bench/] [verilog/] - Rev 343

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Rev Log message Author Age Path
343 Address miss should not be asserted on short frames olof 4679d 20h /ethmac/trunk/bench/verilog/
342 Added cast to avoid inequality when comparing different data types olof 4679d 20h /ethmac/trunk/bench/verilog/
338 root 5473d 23h /ethmac/trunk/bench/verilog/
335 New directory structure. root 5531d 04h /ethmac/trunk/bench/verilog/
334 Minor fixes for Icarus simulator. igorm 6979d 06h /ethmac/trunk/bench/verilog/
331 Tests for delayed CRC and defer indication added. igorm 7008d 01h /ethmac/trunk/bench/verilog/
318 Latest Ethernet IP core testbench. tadejm 7339d 22h /ethmac/trunk/bench/verilog/
315 Updated testbench. Some more testcases, some repaired. tadejm 7452d 01h /ethmac/trunk/bench/verilog/
302 mbist signals updated according to newest convention markom 7501d 06h /ethmac/trunk/bench/verilog/
299 Artisan RAMs added. mohor 7559d 02h /ethmac/trunk/bench/verilog/
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.		 mohor 7627d 02h /ethmac/trunk/bench/verilog/
281 Tests test_mac_full_duplex_receive 4-7 fixed to proper BD. mohor 7759d 22h /ethmac/trunk/bench/verilog/
279 Underrun test fixed. Many other tests fixed. mohor 7761d 00h /ethmac/trunk/bench/verilog/
274 Backup version. Not fully working. tadejm 7768d 18h /ethmac/trunk/bench/verilog/
267 Full duplex control frames tested. mohor 7824d 22h /ethmac/trunk/bench/verilog/
266 Flow control test almost finished. mohor 7829d 20h /ethmac/trunk/bench/verilog/
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.		 mohor 7830d 12h /ethmac/trunk/bench/verilog/
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.		 mohor 7831d 00h /ethmac/trunk/bench/verilog/
254 Temp version. mohor 7832d 17h /ethmac/trunk/bench/verilog/
252 Just some updates. tadejm 7832d 20h /ethmac/trunk/bench/verilog/
243 Late collision is not reported any more. tadejm 7838d 01h /ethmac/trunk/bench/verilog/
227 Changed BIST scan signals. tadejm 7864d 21h /ethmac/trunk/bench/verilog/
223 Some code changed due to bug fixes. tadejm 7865d 00h /ethmac/trunk/bench/verilog/
216 Bist signals added. mohor 7872d 00h /ethmac/trunk/bench/verilog/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.		 tadejm 7874d 01h /ethmac/trunk/bench/verilog/
194 Full duplex tests modified and testbench bug repaired. tadej 7892d 23h /ethmac/trunk/bench/verilog/
192 Some additional reports added tadej 7894d 20h /ethmac/trunk/bench/verilog/
191 Bug repaired in eth_phy device tadej 7894d 20h /ethmac/trunk/bench/verilog/
189 Simple testbench that includes eth_cop, eth_host and eth_memory modules.
This testbench is used for testing the whole environment. Use tb_ethernet
testbench for testing just the ethernet MAC core (many tests).		 mohor 7894d 21h /ethmac/trunk/bench/verilog/
188 PHY changed. tadej 7895d 18h /ethmac/trunk/bench/verilog/

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