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[/] [ethmac/] [trunk/] [bench/] [verilog/] - Rev 345

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Rev Log message Author Age Path
345 Temporarily disable failing tests olof 4670d 01h /ethmac/trunk/bench/verilog/
344 bit 9 in phy control register is self clearing olof 4676d 03h /ethmac/trunk/bench/verilog/
343 Address miss should not be asserted on short frames olof 4679d 23h /ethmac/trunk/bench/verilog/
342 Added cast to avoid inequality when comparing different data types olof 4679d 23h /ethmac/trunk/bench/verilog/
338 root 5474d 02h /ethmac/trunk/bench/verilog/
335 New directory structure. root 5531d 07h /ethmac/trunk/bench/verilog/
334 Minor fixes for Icarus simulator. igorm 6979d 09h /ethmac/trunk/bench/verilog/
331 Tests for delayed CRC and defer indication added. igorm 7008d 04h /ethmac/trunk/bench/verilog/
318 Latest Ethernet IP core testbench. tadejm 7340d 01h /ethmac/trunk/bench/verilog/
315 Updated testbench. Some more testcases, some repaired. tadejm 7452d 05h /ethmac/trunk/bench/verilog/
302 mbist signals updated according to newest convention markom 7501d 10h /ethmac/trunk/bench/verilog/
299 Artisan RAMs added. mohor 7559d 05h /ethmac/trunk/bench/verilog/
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.		 mohor 7627d 05h /ethmac/trunk/bench/verilog/
281 Tests test_mac_full_duplex_receive 4-7 fixed to proper BD. mohor 7760d 01h /ethmac/trunk/bench/verilog/
279 Underrun test fixed. Many other tests fixed. mohor 7761d 04h /ethmac/trunk/bench/verilog/
274 Backup version. Not fully working. tadejm 7768d 22h /ethmac/trunk/bench/verilog/
267 Full duplex control frames tested. mohor 7825d 01h /ethmac/trunk/bench/verilog/
266 Flow control test almost finished. mohor 7830d 00h /ethmac/trunk/bench/verilog/
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.		 mohor 7830d 15h /ethmac/trunk/bench/verilog/
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.		 mohor 7831d 03h /ethmac/trunk/bench/verilog/

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