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[/] [ethmac/] [trunk/] [bench/] [verilog/] - Rev 349

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Rev Log message Author Age Path
348 Added option to dump VCD files olof 4675d 01h /ethmac/trunk/bench/verilog/
346 Updated project location olof 4675d 04h /ethmac/trunk/bench/verilog/
345 Temporarily disable failing tests olof 4675d 05h /ethmac/trunk/bench/verilog/
344 bit 9 in phy control register is self clearing olof 4681d 07h /ethmac/trunk/bench/verilog/
343 Address miss should not be asserted on short frames olof 4685d 03h /ethmac/trunk/bench/verilog/
342 Added cast to avoid inequality when comparing different data types olof 4685d 03h /ethmac/trunk/bench/verilog/
338 root 5479d 06h /ethmac/trunk/bench/verilog/
335 New directory structure. root 5536d 11h /ethmac/trunk/bench/verilog/
334 Minor fixes for Icarus simulator. igorm 6984d 13h /ethmac/trunk/bench/verilog/
331 Tests for delayed CRC and defer indication added. igorm 7013d 08h /ethmac/trunk/bench/verilog/
318 Latest Ethernet IP core testbench. tadejm 7345d 05h /ethmac/trunk/bench/verilog/
315 Updated testbench. Some more testcases, some repaired. tadejm 7457d 09h /ethmac/trunk/bench/verilog/
302 mbist signals updated according to newest convention markom 7506d 14h /ethmac/trunk/bench/verilog/
299 Artisan RAMs added. mohor 7564d 09h /ethmac/trunk/bench/verilog/
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.		 mohor 7632d 09h /ethmac/trunk/bench/verilog/
281 Tests test_mac_full_duplex_receive 4-7 fixed to proper BD. mohor 7765d 05h /ethmac/trunk/bench/verilog/
279 Underrun test fixed. Many other tests fixed. mohor 7766d 08h /ethmac/trunk/bench/verilog/
274 Backup version. Not fully working. tadejm 7774d 02h /ethmac/trunk/bench/verilog/
267 Full duplex control frames tested. mohor 7830d 05h /ethmac/trunk/bench/verilog/
266 Flow control test almost finished. mohor 7835d 04h /ethmac/trunk/bench/verilog/

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