OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [bench/] [verilog/] - Rev 355

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.
mohor 7851d 13h /ethmac/trunk/bench/verilog/
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.
mohor 7852d 01h /ethmac/trunk/bench/verilog/
254 Temp version. mohor 7853d 19h /ethmac/trunk/bench/verilog/
252 Just some updates. tadejm 7853d 21h /ethmac/trunk/bench/verilog/
243 Late collision is not reported any more. tadejm 7859d 02h /ethmac/trunk/bench/verilog/
227 Changed BIST scan signals. tadejm 7885d 22h /ethmac/trunk/bench/verilog/
223 Some code changed due to bug fixes. tadejm 7886d 01h /ethmac/trunk/bench/verilog/
216 Bist signals added. mohor 7893d 02h /ethmac/trunk/bench/verilog/
209 Just back-up; not completed testbench and some testcases are not
wotking properly yet.
tadejm 7895d 02h /ethmac/trunk/bench/verilog/
194 Full duplex tests modified and testbench bug repaired. tadej 7914d 01h /ethmac/trunk/bench/verilog/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.