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Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [bench/] [verilog/] - Rev 364

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Rev Log message Author Age Path
364 Renamed eth_top.v to ethmac.v to fit better into OpenCores structure olof 4703d 01h /ethmac/trunk/bench/verilog/
356 Rename eth_defines.v to ethmac_defines.v to fit better into OpenCores project structure olof 4708d 03h /ethmac/trunk/bench/verilog/
348 Added option to dump VCD files olof 4725d 02h /ethmac/trunk/bench/verilog/
346 Updated project location olof 4725d 04h /ethmac/trunk/bench/verilog/
345 Temporarily disable failing tests olof 4725d 06h /ethmac/trunk/bench/verilog/
344 bit 9 in phy control register is self clearing olof 4731d 08h /ethmac/trunk/bench/verilog/
343 Address miss should not be asserted on short frames olof 4735d 04h /ethmac/trunk/bench/verilog/
342 Added cast to avoid inequality when comparing different data types olof 4735d 04h /ethmac/trunk/bench/verilog/
338 root 5529d 07h /ethmac/trunk/bench/verilog/
335 New directory structure. root 5586d 12h /ethmac/trunk/bench/verilog/
334 Minor fixes for Icarus simulator. igorm 7034d 14h /ethmac/trunk/bench/verilog/
331 Tests for delayed CRC and defer indication added. igorm 7063d 09h /ethmac/trunk/bench/verilog/
318 Latest Ethernet IP core testbench. tadejm 7395d 06h /ethmac/trunk/bench/verilog/
315 Updated testbench. Some more testcases, some repaired. tadejm 7507d 09h /ethmac/trunk/bench/verilog/
302 mbist signals updated according to newest convention markom 7556d 14h /ethmac/trunk/bench/verilog/
299 Artisan RAMs added. mohor 7614d 10h /ethmac/trunk/bench/verilog/
286 Define file in eth_cop.v is changed to eth_defines.v. Some defines were
moved from tb_eth_defines.v to eth_defines.v.
mohor 7682d 10h /ethmac/trunk/bench/verilog/
281 Tests test_mac_full_duplex_receive 4-7 fixed to proper BD. mohor 7815d 06h /ethmac/trunk/bench/verilog/
279 Underrun test fixed. Many other tests fixed. mohor 7816d 08h /ethmac/trunk/bench/verilog/
274 Backup version. Not fully working. tadejm 7824d 02h /ethmac/trunk/bench/verilog/
267 Full duplex control frames tested. mohor 7880d 06h /ethmac/trunk/bench/verilog/
266 Flow control test almost finished. mohor 7885d 05h /ethmac/trunk/bench/verilog/
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.
mohor 7885d 20h /ethmac/trunk/bench/verilog/
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.
mohor 7886d 08h /ethmac/trunk/bench/verilog/
254 Temp version. mohor 7888d 02h /ethmac/trunk/bench/verilog/
252 Just some updates. tadejm 7888d 04h /ethmac/trunk/bench/verilog/
243 Late collision is not reported any more. tadejm 7893d 09h /ethmac/trunk/bench/verilog/
227 Changed BIST scan signals. tadejm 7920d 05h /ethmac/trunk/bench/verilog/
223 Some code changed due to bug fixes. tadejm 7920d 08h /ethmac/trunk/bench/verilog/
216 Bist signals added. mohor 7927d 09h /ethmac/trunk/bench/verilog/

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