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[/] [ethmac/] [trunk/] [bench/] [verilog/] - Rev 364

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Rev Log message Author Age Path
267 Full duplex control frames tested. mohor 7873d 19h /ethmac/trunk/bench/verilog/
266 Flow control test almost finished. mohor 7878d 17h /ethmac/trunk/bench/verilog/
263 test_mac_full_duplex_flow_control tests pretty much finished.
TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL
FRM. AT 4 TX BD ( 10Mbps ) finished.
TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION
TURNED OFF AT ONE RX BD ( 10Mbps ) finished.
mohor 7879d 09h /ethmac/trunk/bench/verilog/
260 test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame
finished.
mohor 7879d 21h /ethmac/trunk/bench/verilog/
254 Temp version. mohor 7881d 15h /ethmac/trunk/bench/verilog/
252 Just some updates. tadejm 7881d 17h /ethmac/trunk/bench/verilog/
243 Late collision is not reported any more. tadejm 7886d 22h /ethmac/trunk/bench/verilog/
227 Changed BIST scan signals. tadejm 7913d 18h /ethmac/trunk/bench/verilog/
223 Some code changed due to bug fixes. tadejm 7913d 21h /ethmac/trunk/bench/verilog/
216 Bist signals added. mohor 7920d 21h /ethmac/trunk/bench/verilog/

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