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[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_ethernet.v] - Rev 263

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Rev	Log message	Author	Age	Path
263	test_mac_full_duplex_flow_control tests pretty much finished. TEST 0: INSERT CONTROL FRM. WHILE TRANSMITTING NORMAL FRM. AT 4 TX BD ( 10Mbps ) finished. TEST 2: RECEIVE CONTROL FRAMES WITH PASSALL OPTION TURNED OFF AT ONE RX BD ( 10Mbps ) finished.	mohor	7832d 04h	/ethmac/trunk/bench/verilog/tb_ethernet.v
260	test_mac_full_duplex_flow test 0 finished. Sending the control (PAUSE) frame finished.	mohor	7832d 16h	/ethmac/trunk/bench/verilog/tb_ethernet.v
254	Temp version.	mohor	7834d 10h	/ethmac/trunk/bench/verilog/tb_ethernet.v
252	Just some updates.	tadejm	7834d 13h	/ethmac/trunk/bench/verilog/tb_ethernet.v
243	Late collision is not reported any more.	tadejm	7839d 17h	/ethmac/trunk/bench/verilog/tb_ethernet.v
227	Changed BIST scan signals.	tadejm	7866d 13h	/ethmac/trunk/bench/verilog/tb_ethernet.v
223	Some code changed due to bug fixes.	tadejm	7866d 16h	/ethmac/trunk/bench/verilog/tb_ethernet.v
209	Just back-up; not completed testbench and some testcases are not wotking properly yet.	tadejm	7875d 17h	/ethmac/trunk/bench/verilog/tb_ethernet.v
194	Full duplex tests modified and testbench bug repaired.	tadej	7894d 16h	/ethmac/trunk/bench/verilog/tb_ethernet.v
192	Some additional reports added	tadej	7896d 12h	/ethmac/trunk/bench/verilog/tb_ethernet.v
182	Full duplex test improved.	tadej	7898d 12h	/ethmac/trunk/bench/verilog/tb_ethernet.v
181	MIIM test look better.	mohor	7898d 15h	/ethmac/trunk/bench/verilog/tb_ethernet.v
180	Bench outputs data to display every 128 bytes.	mohor	7901d 11h	/ethmac/trunk/bench/verilog/tb_ethernet.v
179	Beautiful tests merget together	mohor	7901d 12h	/ethmac/trunk/bench/verilog/tb_ethernet.v
178	Rearanged testcases	mohor	7901d 12h	/ethmac/trunk/bench/verilog/tb_ethernet.v
177	Bug in MIIM fixed.	mohor	7901d 16h	/ethmac/trunk/bench/verilog/tb_ethernet.v
170	Headers changed.	mohor	7901d 18h	/ethmac/trunk/bench/verilog/tb_ethernet.v
169	New testbench. Thanks to Tadej M - "The Spammer".	mohor	7901d 18h	/ethmac/trunk/bench/verilog/tb_ethernet.v
158	Typo fixed.	mohor	7906d 14h	/ethmac/trunk/bench/verilog/tb_ethernet.v
156	Valid testbench.	mohor	7908d 19h	/ethmac/trunk/bench/verilog/tb_ethernet.v
121	gsr added for use when ETH_XILINX_RAMB4 define is set.	mohor	7953d 14h	/ethmac/trunk/bench/verilog/tb_ethernet.v
117	Clock mrx_clk set to 2.5 MHz.	mohor	7957d 16h	/ethmac/trunk/bench/verilog/tb_ethernet.v
116	Testing environment also includes traffic cop, memory interface and host interface.	mohor	7957d 16h	/ethmac/trunk/bench/verilog/tb_ethernet.v

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[/] [ethmac/] [trunk/] [bench/] [verilog/] [tb_ethernet.v] - Rev 263

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